Nano100(A)
Master/Slave up to 1Mbit/s
Bi-directional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption
of serial data on the bus
Serial clock synchronization allowing devices with different bit rates to
communicate via one serial bus
Serial clock synchronization used as a handshake mechanism to suspend
and resume serial transfer
Built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus
hangs up and timer-out counter overflows
Programmable clocks allow versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition (four slave addresses with mask
option)
I2S
Interface with external audio CODEC
Operated as either Master or Slave mode
Capable of handling 8, 16, 24 and 32 bit word sizes
Supports Mono and stereo audio data
Supports I2S and MSB justified data format
Provides two 8 word FIFO data buffers: one for transmitting and the other for
receiving
Generates interrupt requests when buffer levels cross a programmable
boundary
Supports two PDMA requests: one for transmitting and the other for receiving
ADC
12-bit SAR ADC with 800K SPS
Up to 8-ch single-end input from external pin.
One internal channel from AVDD, AVSS, Temp sensor, and internal reference
voltage.
Supports single scan, single cycle scan, and continuous scan modes
Each channel with individual result register
Only scan on enabled channels
Threshold voltage detection (comparator function)
Conversion start by software programming or external input
Supports PDMA mode
Supports up to four timer time-out events (TMR0, TMR1, TMR2, TMR3) to
enable ADC
SmartCard (SC)
Mar 31, 2015
Page 17 of 95
Revision V1.00
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