Nano100(A)
2.2 Nano120 Features – USB Connectivity Line
Core
ARM® Cortex™-M0 core running up to 32 MHz
One 24-bit system timer
Supports Low Power Sleep mode
Single-cycle 32-bit hardware multiplier
NVIC for the 32 interrupt inputs, each with 4-levels of priority
Serial Wire Debug supports with 2 watchpoints/4 breakpoints
Brown-out
Built-in 2.5V/2.0V/1.7V BOD for wide operating voltage range operation
Flash EPROM Memory
Runs up to 32 MHz with zero wait state for discontinuous address read access.
64K/32K bytes application program memory (APROM)
4KB in system programming (ISP) loader program memory (LDROM)
Programmable data flash start address and memory size with 512 bytes page
erase unit
In System Program (ISP)/In Application Program (IAP) to update on chip Flash
EPROM
SRAM Memory
16K/8K bytes embedded SRAM
Support PDMA mode
DMA: Support 5 channels: one VDMA channel and 4 PDMA channels
VDMA
Memory-to-memory transfer
Support block transfer with stride
Support word/half-word/byte boundary address
Support address direction: increment and decrement
PDMA
Peripheral-to-memory, memory-to-peripheral, and memory-to-memory
transfer
Support word boundary address
Support word alignment transfer length in memory-to-memory mode
Support word/half-word/byte alignment transfer length in peripheral-to-
memory and memory-to-peripheral mode
Support word/half-word/byte transfer data width from/to peripheral
Support address: increment, fixed, and wrap around
Clock Control
Flexible selection for different applications
Mar 31, 2015
Page 14 of 95
Revision V1.00
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