Nano100(A)
I2C
Up to two sets of I2C device
Master/Slave up to 1 Mbit/s
Bi-directional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of
serial data on the bus
Serial clock synchronization allows devices with different bit rates to
communicate via one serial bus
Serial clock synchronization used as a handshake mechanism to suspend and
resume serial transfer
Built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs
up and timer-out counter overflows
I2S
Programmable clocks allowing for versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition (four slave addresses with mask option)
Interface with external audio CODEC
Operated as either Master or Slave mode
Capable of handling 8, 16, 24 and 32 bit word sizes
Supports Mono and stereo audio data
Supports I2S and MSB justified data format
Provides two 8 word FIFO data buffers: one for transmitting and the other for
receiving
Generates interrupt requests when buffer levels cross a programmable
boundary
Supports two PDMA requests: one for transmitting and the other for receiving
ADC
12-bit SAR ADC
Up to 8-ch single-ended input from external pin
One internal channel from AVDD, AVSS, Temp sensor, and internal reference
voltage
Supports Single Scan, Single Cycle Scan, and Continuous Scan mode
Each channel with individual result register
Only scan on enabled channels
Threshold voltage detection (comparator function)
Conversion started by software programming or external input
Supports PDMA mode
Supports up to four timer time-out events (TRM0_CH0, TMR0_CH1, TMR1_CH0
Mar 31, 2015
Page 12 of 95
Revision V1.00
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