NAND01G-B2B, NAND02G-B2C
Device operations
6.8.4
Cache program error bit (SR1)
The cache program error bit can be used to identify if the previous page (page N-1) has been
successfully programmed or not in a cache program operation. SR1 is set to ’1’ when the
cache program operation has failed to program the previous page (page N-1) correctly. If
SR1 is set to ‘0’ the operation has completed successfully.
The cache program error bit is only valid during cache program operations, during other
operations it is don’t care.
6.8.5
6.8.6
Error bit (SR0)
The error bit is used to identify if any errors have been detected by the P/E/R controller. The
error bit is set to ’1’ when a program or erase operation has failed to write the correct data to
the memory. If the error bit is set to ‘0’ the operation has completed successfully. The error
bit SR0, in a cache program operation, indicates a failure on page N.
SR4, SR3 and SR2 are reserved
Table 13. Status register bits
Bit
Name
Logic level
Definition
'1'
Not protected
Protected
SR7
Write protection
'0'
'1'
P/E/R C inactive, device ready
Program/ erase/ read
controller
'0'
P/E/R C active, device busy
SR6
'1'
Cache register ready (cache operation only)
Cache register busy (cache operation only)
P/E/R C inactive, device ready
Cache ready/busy
'0'
'1'
Program/ erase/ read
controller(1)
SR5
SR4, SR3, SR2
SR1
'0'
P/E/R C active, device busy
Reserved
Don’t care
'1'
'0'
‘1’
‘0’
‘1’
‘0’
Page N-1 failed in cache program operation
Page N-1 programmed successfully
Error – operation failed
Cache program error(2)
Generic error
No Error – operation successful
SR0
Page N failed in cache program operation
Page N programmed successfully
Cache program error
1. Only valid for cache program operations, for other operations it is same as SR6.
2. Only valid for cache operations, for other operations it is don’t care.
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NUMONYX [ NUMONYX B.V ]
