欢迎访问ic37.com |
会员登录 免费注册
发布采购

M25PE80-VMN6P 参数 Datasheet PDF下载

M25PE80-VMN6P图片预览
型号: M25PE80-VMN6P
PDF下载: 下载PDF文件 查看货源
内容描述: 8兆位,页擦除串行闪存与字节变性, 75兆赫的SPI总线,标准引脚 [8-Mbit, page-erasable serial flash memory with byte alterability, 75 MHz SPI bus, standard pinout]
分类和应用: 闪存内存集成电路
文件页数/大小: 66 页 / 1387 K
品牌: NUMONYX [ NUMONYX B.V ]
 浏览型号M25PE80-VMN6P的Datasheet PDF文件第36页浏览型号M25PE80-VMN6P的Datasheet PDF文件第37页浏览型号M25PE80-VMN6P的Datasheet PDF文件第38页浏览型号M25PE80-VMN6P的Datasheet PDF文件第39页浏览型号M25PE80-VMN6P的Datasheet PDF文件第41页浏览型号M25PE80-VMN6P的Datasheet PDF文件第42页浏览型号M25PE80-VMN6P的Datasheet PDF文件第43页浏览型号M25PE80-VMN6P的Datasheet PDF文件第44页  
Instructions  
M25PE80  
6.12  
Page erase (PE)  
The page erase (PE) instruction sets to ‘1’ (FFh) all bits inside the chosen page. Before it  
can be accepted, a write enable (WREN) instruction must previously have been executed.  
After the write enable (WREN) instruction has been decoded, the device sets the write  
enable latch (WEL).  
The page erase (PE) instruction is entered by driving Chip Select (S) Low, followed by the  
instruction code, and three address bytes on serial data input (D). Any address inside the  
page is a valid address for the page erase (PE) instruction. Chip Select (S) must be driven  
Low for the entire duration of the sequence.  
The instruction sequence is shown in Figure 18.  
Chip Select (S) must be driven High after the eighth bit of the last address byte has been  
latched in, otherwise the page erase (PE) instruction is not executed. As soon as Chip  
Select (S) is driven High, the self-timed page erase cycle (whose duration is t ) is initiated.  
PE  
While the page erase cycle is in progress, the status register may be read to check the value  
of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed  
page erase cycle, and is 0 when it is completed. At some unspecified time before the cycle  
is complete, the write enable latch (WEL) bit is reset.  
A page erase (PE) instruction applied to a page that is hardware or software protected is not  
executed.  
Any page erase (PE) instruction, while an erase, program or write cycle is in progress, is  
rejected without having any effects on the cycle that is in progress.  
If Reset (Reset) is driven Low while a page erase (PE) cycle is in progress, the page erase  
cycle is interrupted and the programmed data may be corrupted (see Table 15: Device  
status after a Reset Low pulse). On Reset going Low, the device enters the reset mode and  
a time of t  
is then required before the device can be re-selected by driving Chip Select  
RHSL  
(S) Low. For the value of t  
see Table 26: Timings after a Reset Low pulse in Section 11:  
RHSL  
DC and AC parameters.  
Figure 18. Page erase (PE) instruction sequence  
S
0
1
2
3
4
5
6
7
8
9
29 30 31  
C
D
Instruction  
24-bit address  
23 22  
MSB  
2
0
1
AI04046  
1. Address bits A23 to A20 are don’t care.  
40/66  
 复制成功!