®
Numonyx™ StrataFlash Embedded Memory (J3-65nm)
11.1.1
11.2
Clearing the Status Register
The Clear Status Register command clears the status register. It functions independent
of VPEN. The WSM sets and clears SR[7,6,2], but it sets bits SR[5:3,1] without clearing
them. The Status Register should be cleared before starting a command sequence to
avoid any ambiguity. A device reset also clears the Status Register.
Status Signal
The STATUS (STS) signal can be configured to different states using the STS
Configuration command (Table 12). Once the STS signal has been configured, it
remains in that configuration until another Configuration command is issued or RP# is
asserted low. Initially, the STS signal defaults to RY/BY# operation where RY/BY# low
indicates that the WSM is busy. RY/BY# high indicates that the state machine is ready
for a new operation or suspended. Table 12 displays possible STS configurations.
To reconfigure the STATUS (STS) signal to other modes, the Configuration command is
given followed by the desired configuration code. The three alternate configurations are
all pulse mode for use as a system interrupt as described in the following paragraphs.
For these configurations, bit 0 controls Erase Complete interrupt pulse, and bit 1
controls Program Complete interrupt pulse. Supplying the 00h configuration code with
the Configuration command resets the STS signal to the default RY/BY# level mode.
The Configuration command may only be given when the device is not busy or
suspended. Check SR.7 for device status. An invalid configuration code will result in
SR.4 and SR.5 being set.
Note:
STS Pulse mode is not supported in the Clear Lock Bits and Set Lock Bit commands.
December 2008
319942-02
Datasheet
31
NUMONYX [ NUMONYX B.V ]
