14.0 USART (Continued)
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FIGURE 21. USART Block Diagram
14.1 USART CONTROL AND STATUS REGISTERS
PEN: This bit enables/disables Parity (7- and 8-bit modes
only). Read/Write, cleared on reset.
The operation of the USART is programmed through three
registers: ENU, ENUR and ENUI.
PEN = 0
PEN = 1
Parity disabled.
Parity enabled.
14.2 DESCRIPTION OF USART REGISTER BITS
PSEL1, PSEL0: Parity select bits. Read/Write, cleared on
reset.
ENU—USART CONTROL AND STATUS REGISTER (Ad-
dress at 0BA)
PSEL1 = 0, PSEL0 = 0
PSEL1 = 0, PSEL1 = 1
PSEL1 = 1, PSEL0 = 0
PSEL1 = 1, PSEL1 = 1
Odd Parity (if Parity enabled)
Even Parity (if Parity enabled)
Mark(1) (if Parity enabled)
Space(0) (if Parity enabled)
PEN PSEL1 XBIT9/ CHL1 CHL0 ERR RBFL TBMT
PSEL0
Bit 7
Bit 0
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