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COP8AME9EMW8 参数 Datasheet PDF下载

COP8AME9EMW8图片预览
型号: COP8AME9EMW8
PDF下载: 下载PDF文件 查看货源
内容描述: 8位CMOS闪存微控制器,具有8K内存,双通道运算放大器,虚拟EEROM ,温度传感器, 10位A / D和掉电复位 [8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEROM, Temperature Sensor,10-Bit A/D and Brownout Reset]
分类和应用: 闪存传感器温度传感器微控制器和处理器外围集成电路运算放大器光电二极管时钟
文件页数/大小: 83 页 / 908 K
品牌: NSC [ National Semiconductor ]
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13.5.1 Low Speed HALT Mode  
13.0 Power Saving Features  
The fully static architecture of this device allows the state of  
the microcontroller to be frozen. Because the low speed  
oscillator draws very minimal operating current, it will be left  
running in the low speed HALT mode. However, the IDLE  
Timer will not be running. This also allows for a faster exit  
from HALT. The processor can be forced to exit the HALT  
mode and resume normal operation at any time.  
(Continued)  
The IDLE mode uses the on-chip IDLE Timer (Timer T0) to  
keep track of elapsed time in the IDLE state. The IDLE Timer  
runs continuously at the low speed clock rate, whether or not  
the device is in the IDLE mode. Each time the bit of the timer  
associated with the selected window toggles, the T0PND bit  
is set, an interrupt is generated (if enabled), and the device  
exits the IDLE mode if in that mode. If the IDLE Timer  
interrupt is enabled, the interrupt is serviced before execu-  
tion of the main program resumes. (However, the instruction  
which was started as the part entered the IDLE mode is  
completed before the interrupt is serviced. This instruction  
should be a NOP which should follow the enter IDLE instruc-  
tion.) The user must reset the IDLE Timer pending flag  
(T0PND) before entering the IDLE mode.  
During normal operation, the actual power consumption de-  
pends heavily on the clock speed and operating voltage  
used in an application and is shown in the Electrical Speci-  
fications. In the HALT mode, the device only draws a small  
leakage current, plus current for the BOR feature, plus the  
32 kHz oscillator current, plus any current necessary for  
driving the outputs. Since total power consumption is af-  
fected by the amount of current required to drive the outputs,  
all I/Os should be configured to draw minimal current prior to  
entering the HALT mode, if possible.  
As with the HALT mode, this device can also be returned to  
normal operation with a Multi-Input Wake-up input.  
13.5.1.1 Entering The Low Speed Halt Mode  
The IDLE Timer cannot be started or stopped under software  
control, and it is not memory mapped, so it cannot be read or  
written by the software. Its state upon Reset is unknown.  
Therefore, if the device is put into the IDLE mode at an  
arbitrary time, it will stay in the IDLE mode for somewhere  
between 30 µs and the selected time period.  
The device enters the HALT mode under software control  
when the Port G data register bit 7 is set to 1. All processor  
action stops in the middle of the next instruction cycle, and  
power consumption is reduced to a very low level. In order to  
expedite exit from HALT, the low speed oscillator is left  
running when the device is Halted in the Low Speed mode.  
However, the IDLE Timer will not be clocked.  
In order to precisely time the duration of the IDLE state, entry  
into the IDLE mode must be ”synchronized to the state of the  
IDLE Timer. The best way to do this is to use the IDLE Timer  
interrupt, which occurs on every underflow of the bit of the  
IDLE Timer which is associated with the selected window.  
Another method is to poll the state of the IDLE Timer pending  
bit T0PND, which is set on the same occurrence. The Idle  
Timer interrupt is enabled by setting bit T0EN in the ICNTRL  
register.  
13.5.1.2 Exiting The Low Speed Halt Mode  
When the HALT mode is entered by setting bit 7 of the Port  
G data register, there is a choice of methods for exiting the  
HALT mode: a chip Reset using the RESET pin or a Multi-  
Input Wake-up. The Reset method and Multi-Input Wake-up  
method can be used with any clock option, but the availabil-  
ity of the G7 input is dependent on the clock option.  
Any time the IDLE Timer window length is changed there is  
the possibility of generating a spurious IDLE Timer interrupt  
by setting the T0PND bit. The user is advised to disable  
IDLE Timer interrupts prior to changing the value of the  
ITSEL bits of the ITMR Register and then clear the T0PND  
bit before attempting to synchronize operation to the IDLE  
Timer.  
13.5.1.3 HALT Exit Using Reset  
A device Reset, which is invoked by a low-level signal on the  
RESET input pin, takes the device out of the Low Speed  
mode and puts it into the High Speed mode.  
13.5.1.4 HALT Exit Using Multi-Input Wake-up  
Note: As with the HALT mode, it is necessary to program two  
NOP’s to allow clock resynchronization upon return from the  
IDLE mode. The NOP’s are placed either at the beginning of  
the IDLE Timer interrupt routine or immediately following the  
“enter IDLE mode” instruction.  
The device can be brought out of the HALT mode by a  
transition received on one of the available Wake-up pins.  
The pins used and the types of transitions sensed on the  
Multi-input pins are software programmable. For information  
on programming and using the Multi-Input Wake-up feature,  
refer to the Multi-Input Wake-up section.  
For more information on the IDLE Timer and its associated  
interrupt, see the description in the Timers section.  
As the low speed oscillator is left running, there is no start up  
delay when exiting the low speed halt mode, regardless of  
the state of the CLKDLY bit.  
13.5 LOW SPEED MODE OPERATION  
This mode of operation allows for low speed operation of the  
core clock and low speed operation of the Idle Timer. Be-  
cause the low speed oscillator draws very little operating  
current, and also to expedite restarting from HALT mode, the  
low speed oscillator is left on at all times in this mode,  
including HALT mode. This is the lowest power mode of  
operation on the device. This mode can only be entered from  
the Dual Clock mode.  
Note: To ensure accurate operation upon start-up of the  
device using Multi-Input Wake-up, the instruction in the ap-  
plication program used for entering the HALT mode should  
be followed by two consecutive NOP (no-operation) instruc-  
tions.  
13.5.1.5 Options  
This device has two options associated with the HALT mode.  
The first option enables the HALT mode feature, while the  
second option disables HALT mode operation. Selecting the  
disable HALT mode option will cause the microcontroller to  
ignore any attempts to HALT the device under software  
control. See the Option section for more details on this  
option bit.  
To enter the Low Speed mode, the following sequence must  
be followed using two separate instructions:  
1. Software sets the CCKSEL bit to 1.  
2. Software clears the HSON bit to 0.  
Since the low speed oscillator is already running, there is no  
clock startup delay.  
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