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COP8AME9EMW8 参数 Datasheet PDF下载

COP8AME9EMW8图片预览
型号: COP8AME9EMW8
PDF下载: 下载PDF文件 查看货源
内容描述: 8位CMOS闪存微控制器,具有8K内存,双通道运算放大器,虚拟EEROM ,温度传感器, 10位A / D和掉电复位 [8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEROM, Temperature Sensor,10-Bit A/D and Brownout Reset]
分类和应用: 闪存传感器温度传感器微控制器和处理器外围集成电路运算放大器光电二极管时钟
文件页数/大小: 83 页 / 908 K
品牌: NSC [ National Semiconductor ]
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be set or reset for the desired edge selects, followed by the  
associated WKPND bits being cleared.  
13.0 Power Saving Features  
(Continued)  
This same procedure should be used following reset, since  
the L port inputs are left floating as a result of reset.  
13.6 MULTI-INPUT WAKE-UP  
The Multi-Input Wake-up feature is used to return (wake-up)  
the device from either the HALT or IDLE modes. Alternately  
Multi-Input Wake-up/Interrupt feature may also be used to  
generate up to 8 edge selectable external interrupts.  
The occurrence of the selected trigger condition for Multi-  
Input Wake-up is latched into a pending register called  
WKPND. The respective bits of the WKPND register will be  
set on the occurrence of the selected trigger edge on the  
corresponding Port L pin. The user has the responsibility of  
clearing these pending flags. Since WKPND is a pending  
register for the occurrence of selected wake-up conditions,  
the device will not enter the HALT mode if any Wake-up bit is  
both enabled and pending. Consequently, the user must  
clear the pending flags before attempting to enter the HALT  
mode.  
Figure 20 shows the Multi-Input Wake-up logic.  
The Multi-Input Wake-up feature utilizes the L Port. The user  
selects which particular L port bit (or combination of L Port  
bits) will cause the device to exit the HALT or IDLE modes.  
The selection is done through the register WKEN. The reg-  
ister WKEN is an 8-bit read/write register, which contains a  
control bit for every L port bit. Setting a particular WKEN bit  
enables a Wake-up from the associated L port pin.  
WKEN and WKEDG are all read/write registers, and are  
cleared at reset. WKPND register contains random value  
after reset.  
The user can select whether the trigger condition on the  
selected L Port pin is going to be either a positive edge (low  
to high transition) or a negative edge (high to low transition).  
This selection is made via the register WKEDG, which is an  
8-bit control register with a bit assigned to each L Port pin.  
Setting the control bit will select the trigger condition to be a  
negative edge on that particular L Port pin. Resetting the bit  
selects the trigger condition to be a positive edge. Changing  
an edge select entails several steps in order to avoid a  
Wake-up condition as a result of the edge change. First, the  
associated WKEN bit should be reset, followed by the edge  
select change in WKEDG. Next, the associated WKPND bit  
should be cleared, followed by the associated WKEN bit  
being re-enabled.  
14.0 USART  
The device contains a full-duplex software programmable  
USART. The USART (Figure 21) consists of a transmit shift  
register, a receive shift register and seven addressable reg-  
isters, as follows: a transmit buffer register (TBUF), a re-  
ceiver buffer register (RBUF), a USART control and status  
register (ENU), a USART receive control and status register  
(ENUR), a USART interrupt and clock source register  
(ENUI), a prescaler select register (PSR) and baud (BAUD)  
register. The ENU register contains flags for transmit and  
receive functions; this register also determines the length of  
the data frame (7, 8 or 9 bits), the value of the ninth bit in  
transmission, and parity selection bits. The ENUR register  
flags framing, data overrun, parity errors and line breaks  
while the USART is receiving.  
An example may serve to clarify this procedure. Suppose we  
wish to change the edge select from positive (low going high)  
to negative (high going low) for L Port bit 5, where bit 5 has  
previously been enabled for an input interrupt. The program  
would be as follows:  
Other functions of the ENUR register include saving the  
ninth bit received in the data frame, enabling or disabling the  
USART’s attention mode of operation and providing addi-  
tional receiver/transmitter status information via RCVG and  
XMTG bits. The determination of an internal or external clock  
source is done by the ENUI register, as well as selecting the  
number of stop bits and enabling or disabling transmit and  
receive interrupts. A control flag in this register can also  
select the USART mode of operation: asynchronous or  
synchronous.  
RBIT 5, WKEN  
; Disable MIWU  
SBIT 5, WKEDG ; Change edge polarity  
RBIT 5, WKPND ; Reset pending flag  
SBIT 5, WKEN  
; Enable MIWU  
If the L port bits have been used as outputs and then  
changed to inputs with Multi-Input Wake-up/Interrupt, a  
safety procedure should also be followed to avoid wake-up  
conditions. After the selected L port bits have been changed  
from output to input but before the associated WKEN bits are  
enabled, the associated edge select bits in WKEDG should  
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