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COP8AME9EMW8 参数 Datasheet PDF下载

COP8AME9EMW8图片预览
型号: COP8AME9EMW8
PDF下载: 下载PDF文件 查看货源
内容描述: 8位CMOS闪存微控制器,具有8K内存,双通道运算放大器,虚拟EEROM ,温度传感器, 10位A / D和掉电复位 [8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEROM, Temperature Sensor,10-Bit A/D and Brownout Reset]
分类和应用: 闪存传感器温度传感器微控制器和处理器外围集成电路运算放大器光电二极管时钟
文件页数/大小: 83 页 / 908 K
品牌: NSC [ National Semiconductor ]
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As with the HALT mode, this device can also be returned to  
normal operation with a Multi-Input Wake-up input.  
13.0 Power Saving Features  
(Continued)  
The IDLE Timer cannot be started or stopped under software  
control, and it is not memory mapped, so it cannot be read or  
written by the software. Its state upon Reset is unknown.  
Therefore, if the device is put into the IDLE mode at an  
arbitrary time, it will stay in the IDLE mode for somewhere  
between 30 µs and the selected time period.  
13.5.2 Low Speed Idle Mode  
In the IDLE mode, program execution stops and power  
consumption is reduced to a very low level as with the HALT  
mode. However, the low speed oscillator, IDLE Timer (Timer  
T0), and Clock Monitor continue to operate, allowing real  
time to be maintained. The device remains IDLE for a se-  
lected amount of time up to 2 seconds, and then automati-  
cally exits the IDLE mode and returns to normal program  
execution using the low speed clock.  
In order to precisely time the duration of the IDLE state, entry  
into the IDLE mode must be synchronized to the state of the  
IDLE Timer. The best way to do this is to use the IDLE Timer  
interrupt, which occurs on every underflow of the bit of the  
IDLE Timer which is associated with the selected window.  
Another method is to poll the state of the IDLE Timer pending  
bit T0PND, which is set on the same occurrence. The Idle  
Timer interrupt is enabled by setting bit T0EN in the ICNTRL  
register.  
The device is placed in the IDLE mode under software  
control by setting the IDLE bit (bit 6 of the Port G data  
register).  
The IDLE Timer window is selectable from one of five values,  
0.125 seconds, 0.25 seconds, 0.5 seconds, 1 second, and  
2 seconds. Selection of this value is made through the ITMR  
register.  
Any time the IDLE Timer window length is changed there is  
the possibility of generating a spurious IDLE Timer interrupt  
by setting the T0PND bit. The user is advised to disable  
IDLE Timer interrupts prior to changing the value of the  
ITSEL bits of the ITMR Register and then clear the T0PND  
bit before attempting to synchronize operation to the IDLE  
Timer.  
The IDLE mode uses the on-chip IDLE Timer (Timer T0) to  
keep track of elapsed time in the IDLE state. The IDLE Timer  
runs continuously at the low speed clock rate, whether or not  
the device is in the IDLE mode. Each time the bit of the timer  
associated with the selected window toggles, the T0PND bit  
is set, an interrupt is generated (if enabled), and the device  
exits the IDLE mode if in that mode. If the IDLE Timer  
interrupt is enabled, the interrupt is serviced before execu-  
tion of the main program resumes. (However, the instruction  
which was started as the part entered the IDLE mode is  
completed before the interrupt is serviced. This instruction  
should be a NOP which should follow the enter IDLE instruc-  
tion.) The user must reset the IDLE Timer pending flag  
(T0PND) before entering the IDLE mode.  
As with the HALT mode, it is necessary to program two  
NOP’s to allow clock resynchronization upon return from the  
IDLE mode. The NOP’s are placed either at the beginning of  
the IDLE Timer interrupt routine or immediately following the  
“enter IDLE mode” instruction.  
For more information on the IDLE Timer and its associated  
interrupt, see the description in Section 12.1 TIMER T0  
(IDLE TIMER).  
20006324  
FIGURE 20. Multi-Input Wake-Up Logic  
41  
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