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COP8AME9EMW8 参数 Datasheet PDF下载

COP8AME9EMW8图片预览
型号: COP8AME9EMW8
PDF下载: 下载PDF文件 查看货源
内容描述: 8位CMOS闪存微控制器,具有8K内存,双通道运算放大器,虚拟EEROM ,温度传感器, 10位A / D和掉电复位 [8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEROM, Temperature Sensor,10-Bit A/D and Brownout Reset]
分类和应用: 闪存传感器温度传感器微控制器和处理器外围集成电路运算放大器光电二极管时钟
文件页数/大小: 83 页 / 908 K
品牌: NSC [ National Semiconductor ]
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13.3.1.5 Options  
13.0 Power Saving Features  
This device has two options associated with the HALT mode.  
The first option enables the HALT mode feature, while the  
second option disables HALT mode operation. Selecting the  
disable HALT mode option will cause the microcontroller to  
ignore any attempts to HALT the device under software  
control. Note that this device can still be placed in the HALT  
mode by stopping the clock input to the microcontroller, if the  
program memory is masked ROM. See the Option section  
for more details on this option bit.  
(Continued)  
part of the oscillator closed loop.) When the IDLE Timer  
underflows, the clock signals are enabled on the chip, allow-  
ing program execution to proceed. Thus, the delay is equal  
to 256 instruction cycles.  
Note: To ensure accurate operation upon start-up of the  
device using Multi-Input Wake-up, the instruction in the ap-  
plication program used for entering the HALT mode should  
be followed by two consecutive NOP (no-operation) instruc-  
tions.  
20006323  
FIGURE 19. Wake-up from HALT  
13.3.2 High Speed Idle Mode  
As with the HALT mode, this device can also be returned to  
normal operation with a RESET, or with a Multi-Input  
Wake-up input. Upon reset the ITMR register is cleared and  
the ITMR register selects the 4,096 instruction cycle tap of  
the IDLE Timer.  
In the IDLE mode, program execution stops and power  
consumption is reduced to a very low level as with the HALT  
mode. However, the high speed oscillator, IDLE Timer (Timer  
T0), T2 timer (T2HS = 1, T2IDLE = 1), and Clock Monitor  
continue to operate, allowing real time to be maintained. The  
device remains idle for a selected amount of time up to  
65,536 instruction cycles, or 32.768 milliseconds with a 2  
MHz instruction clock frequency, and then automatically ex-  
its the IDLE mode and returns to normal program execution.  
The IDLE Timer cannot be started or stopped under software  
control, and it is not memory mapped, so it cannot be read or  
written by the software. Its state upon Reset is unknown.  
Therefore, if the device is put into the IDLE mode at an  
arbitrary time, it will stay in the IDLE mode for somewhere  
between 1 and the selected number of instruction cycles.  
The device is placed in the IDLE mode under software  
control by setting the IDLE bit (bit 6 of the Port G data  
register).  
In order to precisely time the duration of the IDLE state, entry  
into the IDLE mode must be synchronized to the state of the  
IDLE Timer. The best way to do this is to use the IDLE Timer  
interrupt, which occurs on every underflow of the bit of the  
IDLE Timer which is associated with the selected window.  
Another method is to poll the state of the IDLE Timer pending  
bit T0PND, which is set on the same occurrence. The Idle  
Timer interrupt is enabled by setting bit T0EN in the ICNTRL  
register.  
The IDLE Timer window is selectable from one of five values,  
4k, 8k, 16k, 32k or 64k instruction cycles. Selection of this  
value is made through the ITMR register.  
The IDLE mode uses the on-chip IDLE Timer (Timer T0) to  
keep track of elapsed time in the IDLE state. The IDLE Timer  
runs continuously at the instruction clock rate, whether or not  
the device is in the IDLE mode. Each time the bit of the timer  
associated with the selected window toggles, the T0PND bit  
is set, an interrupt is generated (if enabled), and the device  
exits the IDLE mode if in that mode. If the IDLE Timer  
interrupt is enabled, the interrupt is serviced before execu-  
tion of the main program resumes. (However, the instruction  
which was started as the part entered the IDLE mode is  
completed before the interrupt is serviced. This instruction  
should be a NOP which should follow the enter IDLE instruc-  
tion.) The user must reset the IDLE Timer pending flag  
(T0PND) before entering the IDLE mode.  
Any time the IDLE Timer window length is changed there is  
the possibility of generating a spurious IDLE Timer interrupt  
by setting the T0PND bit. The user is advised to disable  
IDLE Timer interrupts prior to changing the value of the  
ITSEL bits of the ITMR Register and then clear the TOPND  
bit before attempting to synchronize operation to the IDLE  
Timer.  
Note: As with the HALT mode, it is necessary to program two  
NOP’s to allow clock resynchronization upon return from the  
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