•
•
Using the instruction cycle clock (tc)
PWM: TxA Toggle
12.0 Timers (Continued)
12.4 TIMER T2 OPERATION IN IDLE MODE
T2 should not be left in this special mode when entering
HALT. The T2IDLE bit must be reset to 0 before entering the
HALT mode to ensure that T2 remains in the same state
when exiting HALT as it was prior to entering HALT.
Timer T2 has a special mode that allows it to be operated in
IDLE mode. To use this mode, T2 must be configured as a
high speed timer, by setting T2HS = 1, and, also, configured
to run in the IDLE mode by setting the T2IDLE bit to 1 in the
HSTCR register. Table 16 shows the modes of operation
allowed for T2 during the IDLE mode. All the T2 modes are
allowed except the following:
TABLE 16. Timer T2 Mode Control Bits in IDLE Mode
Interrupt A
Source
Interrupt B
Source
Timer
Counts On
Mode
TxC3
TxC2
TxC1
Description
Not Allowed
1
1
0
0
1
0
1
PWM: No TxA
Toggle
Autoreload RA
Autoreload RB
MCLK
0
0
0
0
0
1
0
1
0
External Event
Counter
Timer Underflow Pos. TxB Edge
Timer Underflow Pos. TxB Edge
TxA Pos.
Edge
2
External Event
Counter
TxA Neg.
Edge
Captures:
Pos. TxA Edge
or Timer
Pos. TxB Edge
MCLK
TxA Pos. Edge
TxB Pos. Edge
Captures:
Underflow
1
0
1
1
1
1
0
1
1
Pos. TxA
Pos.TxB
Edge
MCLK
MCLK
MCLK
TxA Pos. Edge
TxB Neg. Edge
Captures:
Edge or Timer
Underflow
3
Neg. TxA
Pos. TxB
Edge
TxA Neg. Edge
TxB Pos. Edge
Captures:
Edge or Timer
Underflow
Neg. TxA
Neg. TxB
Edge
TxA Neg. Edge
TxB Neg. Edge
Edge or Timer
Underflow
12.4.1 Timer T2 Clocking Scheme
Table 17 shows the relationship between the T2 clock, the
Processor clock, and the T0 clock. Note that the T2 clock is
always equal to the processor clock frequency when en-
abled.
TABLE 17. Timer T2 Clocking Scheme
Procesor
Clock
HS Clock
Off
T2 Clock if
T2IDLE = 1
HS Clock
HS Clock
HS Clock
HS Clock
LS Clock
LS Clock
T2 Clock if
T2IDLE = 0
HS Clock
Off
Device Clock Mode
High Speed
Idle Mode
T0 Clock
0
1
0
1
0
1
HS Clock
HS Clock
LS Clock
LS Clock
LS Clock
LS Clock
HS Clock
Off
HS Clock
Off
Dual Clock
LS Clock
Off
LS Clock
Off
Low Speed
35
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