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30151-33 参数 Datasheet PDF下载

30151-33图片预览
型号: 30151-33
PDF下载: 下载PDF文件 查看货源
内容描述: 的Geode ™ GXM处理器与MMX支持集成的x86解决方案 [Geode⑩ GXm Processor Integrated x86 Solution with MMX Support]
分类和应用:
文件页数/大小: 244 页 / 4221 K
品牌: NSC [ National Semiconductor ]
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Signal Definitions (Continued)  
2.2.4 Video Interface Signals (Continued)  
BGA  
SPGA  
Signal Name  
Pin No  
Pin No  
Type  
Description  
CRT_VSYNC  
AA3  
AH2  
O
CRT Vertical Sync  
CRT Vertical Sync establishes the screen refresh rate and verti-  
cal retrace interval for an attached CRT. The polarity is program-  
mable and depends on the display mode.  
FP_HSYNC  
L2  
R4  
O
Flat Panel Horizontal Sync  
Flat Panel Horizontal Sync establishes the line rate and horizon-  
tal retrace interval for a TFT display. Polarity is programmable  
and depends on the display mode.  
This signal is an input to the CS5530. The CS5530 re-drives this  
signal to the flat panel.  
If no flat panel is used in the system, this signal does not need to  
be connected.  
FP_VSYNC  
J1  
P2  
O
Flat Panel Vertical Sync  
Flat Panel Vertical Sync establishes the screen refresh rate and  
vertical retrace interval for a TFT display. Polarity is programma-  
ble and depends on the display mode.  
This signal is an input to the CS5530. The CS5530 re-drives this  
signal to the flat panel.  
If no flat panel is used in the system, this signal does not need to  
be connected.  
ENA_DISP  
VID_RDY  
AD5  
AM6  
O
Display Enable  
Display Enable indicates the active display portion of a scan line  
to the CS5530.  
In a CS5530-based system, this signal is required to be con-  
nected even if there is no TFT panel in the system.  
AD1  
M2  
AK2  
S3  
I
Video Ready  
This input signal indicates that the video FIFO in the CS5530 is  
ready to receive more data.  
VID_VAL  
O
O
Video Valid  
VID_VAL qualifies valid video data to the CS5530.  
Video Data Bus  
VID_DATA[7:0]  
Refer  
to  
Refer  
toTable  
2-5  
When the Video Port is enabled, this bus drives Video (Y-U-V)  
data synchronous to the VID_CLK output.  
PIXEL[17:0]  
Refer  
Refer  
O
Graphics Pixel Data Bus  
toTable toTable  
2-3 2-5  
This bus drives graphics pixel data synchronous to the PCLK  
output.  
Revision 3.1  
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