Signal Definitions (Continued)
2.2.3 Memory Controller Interface Signals (Continued)
BGA
SPGA
Signal Name
Pin No. Pin No.
Type
Description
DQM[7:0]
Refer Refer
O
Data Mask Control Bits
toTable toTable
During memory read cycles, these outputs control whether the
SDRAM output buffers are driven on the MD bus or not. All DQM
signals are asserted during read cycles.
2-3
2-5
During memory write cycles, these outputs control whether or
not MD data will be written into the SDRAM.
DQM[7:0] connect directly to the DQM7-0 pins of each connec-
tor.
CKEA,
CKEB
AF24,
AD16
AL33,
AN23
O
O
Clock Enable
For normal operation CKE is held high. CKE goes low during
Suspend.
SDCLK[3:0]
AE4,
AF5,
AE5,
AF4
AM8,
AK10,
AL7,
SDRAM Clocks
The SDRAM samples all the control, address, and data using
these clocks.
AK8
SDCLK_IN
AE8
AK12
I
SDRAM Clock Input
The GXm processor samples the memory read data on this
clock. Works in conjunction with the SDCLK_OUT signal.
SDCLK_OUT
AF8
AL13
O
SDRAM Clock Output
This output is routed back to SDCLK_IN. The board designer
should vary the length of the board trace to control skew
between SDCLK_IN and SDCLK.
2.2.4 Video Interface Signals
BGA
SPGA
Signal Name
Pin No
Pin No
Type
Description
PCLK
AC1
AJ1
O
Pixel Port Clock
Pixel Port Clock represents the pixel dotclock or a 2x multiple of
the dotclock for some 16-bit-per-pixel modes. It determines the
data transfer rate from the GXm processor to the CS5530.
VID_CLK
DCLK
P1
V4
O
I
Video Clock
Video Clock represents the video port clock to the CS5530. This
pin is only used if the Video Port is enabled.
AB1
AD4
DOT Clock
The DCLK input is driven from the CS5530 and represents the
pixel dot clock. In some cases, such as when displaying 16 BPP
data with an eight-bit-graphics pixel port, this clock will actually
be a 2x multiple of the dotclock.
CRT_HSYNC
W2
AD2
O
CRT Horizontal Sync
CRT Horizontal Sync establishes the line rate and horizontal
retrace interval for an attached CRT. The polarity is programma-
ble and depends on the display mode.
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