Instruction Set (Continued)
Table 9-29. FPU Instruction Set Summary (Continued)
Clock
Count
Notes
FPU Instruction
Opcode
Operation
TOS <--- COS(TOS)
FCOS Function Evaluation: Cos(x)
FDECSTP Decrement Stack pointer
FDIV Floating Point Divide
Top of Stack
D9 FF
D9 F6
92 - 141
4
1
Decrement top of stack pointer
DC [1111 1 n]
ST(n) <--- ST(n) / TOS
24 - 34
24 - 34
24 - 34
24 - 34
24 - 34
80-bit Register
D8 [1111 0 n]
TOS <--- TOS / ST(n)
64-bit Real
DC [mod 110 r/m]
D8 [mod 110 r/m]
DE [1111 1 n]
TOS <--- TOS / M.DR
32-bit Real
TOS <--- TOS / M.SR
FDIVP Floating Point Divide, Pop
FDIVR Floating Point Divide Reversed
Top of Stack
ST(n) <--- ST(n) / TOS; then pop TOS
DC [1111 0 n]
TOS <--- ST(n) / TOS
24 - 34
24 - 34
24 - 34
24 - 34
24 - 34
80-bit Register
D8 [1111 1 n]
ST(n) <--- TOS / ST(n)
64-bit Real
DC [mod 111 r/m]
D8 [mod 111 r/m]
DE [1111 0 n]
TOS <--- M.DR / TOS
32-bit Real
TOS <--- M.SR / TOS
FDIVRP Floating Point Divide Reversed, Pop
FIDIV Floating Point Integer Divide
32-bit Integer
ST(n) <--- TOS / ST(n); then pop TOS
DA [mod 110 r/m]
DE [mod 110 r/m]
TOS <--- TOS / M.SI
TOS <--- TOS / M.WI
34 - 38
34 - 38
16-bit Integer
FIDIVR Floating Point Integer Divide Reversed
32-bit Integer
DA [mod 111 r/m]
DE [mod 111 r/m]
DD [1100 0 n]
D9 F7
TOS <--- M.SI / TOS
TOS <--- M.WI / TOS
TAG(n) <--- Empty
Increment top-of-stack pointer
Wait, then initialize
Initialize
34 - 38
16-bit Integer
34 - 38
FFREE Free Floating Point Register
FINCSTP Increment Stack Pointer
FINIT Initialize FPU
4
2
8
6
(9B)DB E3
FNINIT Initialize FPU
DB E3
FLD Load Data to FPU Register
Top of Stack
D9 [1100 0 n]
Push ST(n) onto stack
Push M.DR onto stack
Push M.SR onto stack
Push M.BCD onto stack
2
64-bit Real
DD [mod 000 r/m]
D9 [mod 000 r/m]
DF [mod 100 r/m]
2
2
32-bit Real
FBLD Load Packed BCD Data to FPU Register
FILD Load Integer Data to FPU Register
64-bit Integer
41 - 45
DF [mod 101 r/m]
DB [mod 000 r/m]
DF [mod 000 r/m]
D9 E8
Push M.LI onto stack
Push M.SI onto stack
Push M.WI onto stack
Push 1.0 onto stack
4 - 8
4 - 6
3 - 6
4
32-bit Integer
16-bit Integer
FLD1 Load Floating Const.= 1.0
FLDCW Load FPU Mode Control Register
FLDENV Load FPU Environment
FLDL2E Load Floating Const.= Log2(e)
FLDL2T Load Floating Const.= Log2(10)
FLDLG2 Load Floating Const.= Log10(2)
FLDLN2 Load Floating Const.= Ln(2)
FLDPI Load Floating Const.= π
FLDZ Load Floating Const.= 0.0
FMUL Floating Point Multiply
Top of Stack
D9 [mod 101 r/m]
D9 [mod 100 r/m]
D9 EA
Ctl Word <--- Memory
Env Regs <--- Memory
Push Log2(e) onto stack
Push Log2(10) onto stack
Push Log10(2) onto stack
Push Loge(2) onto stack
Push π onto stack
4
30
4
D9 E9
4
D9 EC
4
D9 ED
4
D9 EB
4
D9 EE
Push 0.0 onto stack
4
DC [1100 1 n]
ST(n) <--- ST(n) × TOS
4 - 9
4 - 9
4 - 8
4 - 6
4 - 9
80-bit Register
D8 [1100 1 n]
TOS <--- TOS × ST(n)
64-bit Real
DC [mod 001 r/m]
D8 [mod 001 r/m]
DE [1100 1 n]
TOS <--- TOS × M.DR
32-bit Real
TOS <--- TOS × M.SR
FMULP Floating Point Multiply & Pop
FIMUL Floating Point Integer Multiply
32-bit Integer
ST(n) <--- ST(n) × TOS; then pop TOS
DA [mod 001 r/m]
DE [mod 001 r/m]
TOS <--- TOS × M.SI
TOS <--- TOS × M.WI
9 - 11
8 - 10
16-bit Integer
www.national.com
226
Revision 3.1
NSC [ National Semiconductor ]
