Instruction Set (Continued)
Table 9-29. FPU Instruction Set Summary (Continued)
Clock
Count
Notes
FPU Instruction
FNOP No Operation
FPATAN Function Eval: Tan-1(y/x)
FPREM Floating Point Remainder
FPREM1 Floating Point Remainder IEEE
FPTAN Function Eval: Tan(x)
Opcode
Operation
D9 D0
D9 F3
D9 F8
D9 F5
D9 F2
D9 FC
No Operation
2
ST(1) <--- ATAN[ST(1) / TOS]; then pop TOS
TOS <--- Rem[TOS / ST(1)]
TOS <--- Rem[TOS / ST(1)]
TOS <--- TAN(TOS); then push 1.0 onto stack
TOS <--- Round(TOS)
97 - 161
82 - 91
82 - 91
117 - 129
10 - 20
56 - 72
57 - 67
55 - 65
7 - 14
3
1
FRNDINT Round to Integer
FRSTOR Load FPU Environment and Register
FSAVE Save FPU Environment and Register
FNSAVE Save FPU Environment and Register
FSCALE Floating Multiply by 2n
DD [mod 100 r/m]
(9B)DD [mod 110 r/m]
DD [mod 110 r/m]
D9 FD
Restore state
Wait, then save state
Save state
TOS <--- TOS × 2(ST(1))
TOS <--- SIN(TOS)
FSIN Function Evaluation: Sin(x)
D9 FE
76 - 140
145 - 161
1
1
FSINCOS Function Eval.: Sin(x)& Cos(x)
D9 FB
temp <--- TOS;
TOS <--- SIN(temp); then
push COS(temp) onto stack
FSQRT Floating Point Square Root
FST Store FPU Register
Top of Stack
D9 FA
TOS <--- Square Root of TOS
59 - 60
DD [1101 0 n]
ST(n) <--- TOS
M.DR <--- TOS
M.SR <--- TOS
2
2
2
64-bit Real
DD [mod 010 r/m]
D9 [mod 010 r/m]
32-bit Real
FSTP Store FPU Register, Pop
Top of Stack
DB [1101 1 n]
ST(n) <--- TOS; then pop TOS
M.XR <--- TOS; then pop TOS
M.DR <--- TOS; then pop TOS
M.SR <--- TOS; then pop TOS
M.BCD <--- TOS; then pop TOS
2
80-bit Real
DB [mod 111 r/m]
DD [mod 011 r/m]
D9 [mod 011 r/m]
DF [mod 110 r/m]
2
64-bit Real
2
2
32-bit Real
FBSTP Store BCD Data, Pop
FIST Store Integer FPU Register
32-bit Integer
57 - 63
DB [mod 010 r/m]
DF [mod 010 r/m]
M.SI <--- TOS
M.WI <--- TOS
8 - 13
7 - 10
16-bit Integer
FISTP Store Integer FPU Register, Pop
64-bit Integer
DF [mod 111 r/m]
DB [mod 011 r/m]
DF [mod 011 r/m]
(9B)D9 [mod 111 r/m]
D9 [mod 111 r/m]
(9B)D9 [mod 110 r/m]
D9 [mod 110 r/m]
(9B)DD [mod 111 r/m]
DD [mod 111 r/m]
(9B)DF E0
M.LI <--- TOS; then pop TOS
M.SI <--- TOS; then pop TOS
M.WI <--- TOS; then pop TOS
Wait Memory <--- Control Mode Register
Memory <--- Control Mode Register
Wait Memory <--- Env. Registers
Memory <--- Env. Registers
10 - 13
32-bit Integer
8 - 13
16-bit Integer
7 - 10
FSTCW Store FPU Mode Control Register
FNSTCW Store FPU Mode Control Register
FSTENV Store FPU Environment
FNSTENV Store FPU Environment
FSTSW Store FPU Status Register
FNSTSW Store FPU Status Register
FSTSW AX Store FPU Status Register to AX
FNSTSW AX Store FPU Status Register to AX
FSUB Floating Point Subtract
Top of Stack
5
3
14 - 24
12 - 22
Wait Memory <--- Status Register
Memory <--- Status Register
Wait AX <--- Status Register
AX <--- Status Register
6
4
4
2
DF E0
DC [1110 1 n]
ST(n) <--- ST(n) - TOS
4 - 9
4 - 9
4 - 9
4 - 9
4 - 9
80-bit Register
D8 [1110 0 n]
TOS <--- TOS - ST(n
64-bit Real
DC [mod 100 r/m]
D8 [mod 100 r/m]
DE [1110 1 n]
TOS <--- TOS - M.DR
32-bit Real
TOS <--- TOS - M.SR
FSUBP Floating Point Subtract, Pop
FSUBR Floating Point Subtract Reverse
Top of Stack
ST(n) <--- ST(n) - TOS; then pop TOS
DC [1110 0 n]
TOS <--- ST(n) - TOS
4 - 9
4 - 9
4 - 9
4 - 9
4 - 9
80-bit Register
D8 [1110 1 n]
ST(n) <--- TOS - ST(n)
64-bit Real
DC [mod 101 r/m]
D8 [mod 101 r/m]
DE [1110 0 n]
TOS <--- M.DR - TOS
32-bit Real
TOS <--- M.SR - TOS
FSUBRP Floating Point Subtract Reverse, Pop
ST(n) <--- TOS - ST(n); then pop TOS
Revision 3.1
227
www.national.com
NSC [ National Semiconductor ]
