Instruction Set (Continued)
Table 9-31. MMX Instruction Set Summary
MMX Instructions
Opcode
Operation and Clock Count (Latency/Throughput)
EMMS Empty MMX State
MOVD Move Doubleword
Register to MMX Register
MMX Register to Register
Memory to MMX Register
MMX Register to Memory
MOVQ Move Quardword
0F77
Tag Word <--- FFFFh (empties the floating point tag word)
1/1
0F6E [11 mm reg]
0F7E [11 mm reg]
MMX reg [qword] <--move, zero extend-- reg [dword]
reg [qword] <--move-- MMX reg [low dword]
1/1
5/1
1/1
1/1
0F6E [mod mm r/m] MMX regr[qword] <--move, zero extend-- memory[dword]
0F7E [mod mm r/m] Memory [dword] <--move-- MMX reg [low dword]
MMX Register 2 to MMX Register 1
MMX Register 1 to MMX Register 2
Memory to MMX Register
MMX Register to Memory
0F6F [11 mm1 mm2] MMX reg 1 [qword] <--move-- MMX reg 2 [qword]
0F7F [11 mm1 mm2] MMX reg 2 [qword] <--move-- MMX reg 1 [qword]
0F6F [mod mm r/m] MMX reg [qword] <--move-- memory[qword]
0F7F [mod mm r/m] Memory [qword] <--move-- MMX reg [qword]
1/1
1/1
1/1
1/1
PACKSSDW Pack Dword with Signed Saturation
MMX Register 2 to MMX Register 1
Memory to MMX Register
0F6B [11 mm1 mm2] MMX reg 1 [qword] <--packdw, signed sat-- MMX reg 2, MMX reg 1
0F6B [mod mm r/m] MMX reg [qword] <--packdw, signed sat-- memory, MMX reg
1/1
1/1
PACKSSWB Pack Word with Signed Saturation
MMX Register 2 to MMX Register 1
Memory to MMX Register
0F63 [11 mm1 mm2] MMX reg 1 [qword] <--packwb, signed sat-- MMX reg 2, MMX reg 1
0F63 [mod mm r/m] MMX reg [qword] <--packwb, signed sat-- memory, MMX reg
1/1
1/1
PACKUSWB Pack Word with Unsigned Saturation
MMX Register 2 to MMX Register 1
Memory to MMX Register
0F67 [11 mm1 mm2] MMX reg 1 [qword] <--packwb, unsigned sat-- MMX reg 2, MMX reg 1
1/1
1/1
0F67 [mod mm r/m]
MMX reg [qword] <--packwb, unsigned sat-- memory, MMX reg
PADDB Packed Add Byte with Wrap-Around
MMX Register 2 to MMX Register 1
Memory to MMX Register
0FFC [11 mm1 mm2] MMX reg 1 [byte] <---- MMX reg 1 [byte] + MMX reg 2 [byte]
0FFC [mod mm r/m] MMX reg[byte] <---- memory [byte] + MMX reg [byte]
1/1
1/1
PADDD Packed Add Dword with Wrap-Around
MMX Register 2 to MMX Register 1
Memory to MMX Register
0FFE [11 mm1 mm2] MMX reg 1 [sign dword] <---- MMX reg 1 [sign dword] + MMX reg 2 [sign dword] 1/1
0FFE [mod mm r/m] MMX reg [sign dword] <---- memory [sign dword] + MMX reg [sign dword]
1/1
PADDSB Packed Add Signed Byte with Saturation
MMX Register 2 to MMX Register 1
Memory to Register
0FEC [11 mm1 mm2] MMX reg 1 [sign byte] <--sat-- MMX reg 1 [sign byte] + MMX reg 2 [sign byte]
0FEC [mod mm r/m] MMX reg [sign byte] <--sat-- memory [sign byte] + MMX reg [sign byte]
1/1
1/1
PADDSW Packed Add Signed Word with Saturation
MMX Register 2 to MMX Register 1
Memory to Register
0FED [11 mm1 mm2] MMX reg 1 [sign word] <--sat-- MMX reg 1 [sign word] + MMX reg 2 [sign word] 1/1
0FED [mod mm r/m] MMX reg [sign word] <--sat-- memory [sign word] + MMX reg [sign word]
1/1
PADDUSB Add Unsigned Byte with Saturation
MMX Register 2 to MMX Register 1
Memory to Register
0FDC [11 mm1 mm2] MMX reg 1 [byte] <--sat-- MMX reg 1 [byte] + MMX reg 2 [byte]
0FDC [mod mm r/m] MMX reg [byte] <--sat-- memory [byte] + MMX reg [byte]
1/1
1/1
PADDUSW Add Unsigned Word with Saturation
MMX Register 2 to MMX Register 1
Memory to Register
0FDD [11 mm1 mm2] MMX reg 1 [word] <--sat-- MMX reg 1 [word] + MMX reg 2 [word]
0FDD [mod mm r/m] MMX reg [word] <--sat-- memory [word] + MMX reg [word]
1/1
1/1
PADDW Packed Add Word with Wrap-Around
MMX Register 2 to MMX Register 1
Memory to MMX Register
0FFD [11 mm1 mm2] MMX reg 1 [word] <---- MMX reg 1 [word] + MMX reg 2 [word]
1/1
1/1
0FFD [mod mm r/m] MMX reg [word] <---- memory [word] + MMX reg [word]
PAND Bitwise Logical AND
MMX Register 2 to MMX Register 1
Memory to MMX Register
0FDB [11 mm1 mm2] MMX reg 1 [qword] <--logic AND-- MMX reg 1 [qword], MMX reg 2 [qword]
0FDB [mod mm r/m] MMX reg [qword] <--logic AND-- memory [qword], MMX reg [qword]
1/1
PANDN Bitwise Logical AND NOT
MMX Register 2 to MMX Register 1
Memory to MMX Register
0FDF [11 mm1 mm2] MMX reg 1 [qword] <--logic AND -- NOT MMX reg 1 [qword], MMX reg 2 [qword]
0FDF [mod mm r/m] MMX reg [qword] <--logic AND-- NOT MMX reg [qword], Memory [qword]
1/1
1/1
PCMPEQB Packed Byte Compare for Equality
MMX Register 2 with MMX Register 1 0F74 [11 mm1 mm2] MMX reg 1 [byte] <--FFh-- if MMX reg 1 [byte] = MMX reg 2 [byte]
MMX reg 1 [byte]<--00h-- if MMX reg 1 [byte] NOT = MMX reg 2 [byte]
1/1
1/1
Memory with MMX Register
0F74 [mod mm r/m]
MMX reg [byte] <--FFh-- if memory[byte] = MMX reg [byte]
MMX reg [byte] <--00h-- if memory[byte] NOT = MMX reg [byte]
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