Instruction Set (Continued)
Table 9-27. Processor Core Instruction Set Summary (Continued)
Real
Mode
Prot’d Real Prot’d
Mode Mode Mode
Flags
O
F
D
F
I
F
T
F
S
F
Z
F
A
F
P
F
C
F
Clock Count
(Reg/Cache Hit)
Instruction
STC Set Carry Flag
Opcode
Notes
F9
FD
FB
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
-
1
4
6
1
4
6
STD Set Direction Flag
1
-
-
STI Set Interrupt Flag
1
-
m
h
SUB Integer Subtract
Register to Register
2 [10dw] [11 reg r/m]
2 [100w] [mod reg r/m]
2 [101w] [mod reg r/m]
8 [00sw] [mod 101 r/m] ###
2 [110w] ###
x
-
-
-
x
x
x
x
x
1
1
1
1
b
Register to Memory
Memory to Register
1
1
Immediate to Register/Memory
Immediate to Accumulator (short form)
SVDC Save Segment Register and Descriptor
SVLDT Save LDTR and Descriptor
SVTS Save TSR and Descriptor
TEST Test Bits
1
1
1
1
0F 78 [mod sreg3 r/m]
0F 7A [mod 000 r/m]
0F 7C [mod 000 r/m]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
20
20
21
20
20
21
s
s
s
s
s
s
Register/Memory and Register
Immediate Data and Register/Memory
Immediate Data and Accumulator
VERR Verify Read Access
To Register/Memory
8 [010w] [mod reg r/m]
F [011w] [mod 000 r/m] ###
A [100w] ###
0
-
-
-
x
x
u
x
0
1
1
1
1
1
1
b
h
0F 00 [mod 100 r/m]
-
-
-
-
-
x
-
-
-
8
a
a
t
g,h,j,p
g,h,j,p
t
VERW Verify Write Access
To Register/Memory
0F 00 [mod 101 r/m]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
x
-
-
-
-
-
-
-
-
-
-
-
-
-
8
1
WAIT Wait Until FPU Not Busy
WBINVD Write-Back and Invalidate Cache
WRMSR Write to Model Specific Register
XADD Exchange and Add
Register1, Register2
9B
1
0F 09
0F 30
-
23
23
-
0F C[000w] [11 reg2 reg1]
0F C[000w] [mod reg r/m]
x
-
-
-
x
x
x
x
x
2
2
2
2
Memory, Register
XCHG Exchange
Register/Memory with Register
Register with Accumulator
XLAT Translate Byte
8[011w] [mod reg r/m]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
2
5
2
2
5
b,f
b
f,h
h
9[0 reg]
D7
-
-
-
XOR Boolean Exclusive OR
Register to Register
3 [00dw] [11 reg r/m]
3 [000w] [mod reg r/m]
3 [001w] [mod reg r/m]
8 [00sw] [mod 110 r/m] ###
3 [010w] ###
0
x
x
u
x
0
1
1
1
1
1
1
1
1
1
1
h
Register to Memory
Memory to Register
Immediate to Register/Memory
Immediate to Accumulator (short form)
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