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30141-23 参数 Datasheet PDF下载

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型号: 30141-23
PDF下载: 下载PDF文件 查看货源
内容描述: 的Geode ™ GXM处理器与MMX支持集成的x86解决方案 [Geode⑩ GXm Processor Integrated x86 Solution with MMX Support]
分类和应用: 微控制器和处理器外围集成电路微处理器
文件页数/大小: 244 页 / 4221 K
品牌: NSC [ National Semiconductor ]
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Instruction Set (Continued)  
9.5 MMX INSTRUCTION SET  
The CPU is functionally divided into the FPU unit, and the  
integer unit. The FPU has been extended to process both  
MMX instructions and floating point instructions in parallel  
with the integer unit. Revision 3.1  
Table 9-30. MMX Instruction Set Table Legend  
Abbreviation  
Description  
<----  
Result written  
For example, when the integer unit detects a MMX  
instruction, the instruction passes to the FPU unit for exe-  
cution. The integer unit continues to execute instructions  
while the FPU unit executes the MMX instruction. If  
another MMX instruction is encountered, the second  
MMX instruction is placed in the MMX queue. Up to four  
MMX instructions can be queued.  
[11 mm reg]  
mm  
Binary or binary groups of digits  
One of eight 64-bit MMX registers  
A general purpose register  
reg  
<--sat--  
If required, the resultant data is saturated  
to remain in the associated data range  
<--move--  
[byte]  
Source data is moved to result location  
Eight 8-bit bytes are processed in parallel  
Four 16-bit word are processed in parallel  
The MMX instruction set is summarized in Table 9-31 on  
page 230. The abbreviations used in the table are listed in  
Table 9-30.  
[word]  
[dword]  
Two 32-bit double words are processed in  
parallel  
[qword]  
One 64-bit quad word is processed  
[sign xxx]  
The byte, word, double word or quad word  
most significant bit is a sign bit  
mm1, mm2  
mod r/m  
MMX Register 1, MMX Register 2  
Mod and r/m byte encoding (page 6-6 of  
this manual)  
pack  
Source data is truncated or saturated to  
next smaller data size, then concatenated.  
packdw  
Pack two double words from source and  
two double words from destination into four  
words in destination register.  
packwb  
Pack four words from source and four  
words from destination into eight bytes in  
destination register.  
Revision 3.1  
229  
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