Integrated Functions (Continued)
4.6.8.2 PCI Write Transaction
The address phase begins on clock 2 when FRAME# is
asserted. The first and second data phases complete
without delays. During data phase 3, the target inserts
three wait cycles by deasserting TRDY#.
A PCI write transaction is similar to a PCI read transac-
tion, consisting of an address phase and one or more data
phases. Since the master provides both address and
data, no turnaround cycle is required following the
address phase. The data phases work the same for both
read and write transactions. Figure 4-19 illustrates a write
transaction.
For additional information refer to Chapter 3.3.2, Write
Transaction, of the PCI Local Bus Specification, Revision
2.1.
CLK
FRAME#
DATA-3
BE#’s-3
DATA-2
DATA-1
ADDR
AD
BE#’s-2
BUS CMD BE#’s-1
C/BE#
IRDY#
TRDY#
DEVSEL#
DATA
PHASE
DATA
PHASE
DATA
PHASE
ADDR
PHASE
BUS TRANSACTION
Figure 4-19. Basic Write Operation
Revision 3.1
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