Integrated Functions (Continued)
Table 4-40. PCI Configuration Registers (Continued)
Bit
Name
Description
Index 41h
PCI Control Function 2 Register (R/W)
Reserved: Set to 0.
Default Value = 96h
7
6
5
RSVD
RW_CLK
PFS
RAW Clock: A debug signal used to view internal clock operation. 0 = Disable; 1 = Enable.
PERR# forces SERR#: PCI master drives an active SERR# anytime it also drives or receives an active
PERR#: 0 = Disable; 1 = Enable.
4
XWB
SDB
X-Bus to PCI Write Buffer: Enable GXm processor PCI master’s X-Bus write buffers (non-locked mem-
ory cycles are buffered, I/O cycles and lock cycles are not buffered): 0 = Disable; 1 = Enable.
3:2
Slave Disconnect Boundary: PCI slave issues a disconnect with data when it crosses line boundary:
00 = 128 bytes
01 = 256 bytes
10 = 512 bytes
11 = 1024 bytes
Works in conjunction with bit 1.
1
0
SDBE
XWS
Slave Disconnect Boundary Enable:
0 = PCI slave disconnects on boundaries set by bits [3:2].
1 = PCI disconnects on cache line boundary which is 16 bytes.
X-Bus Wait State Enable: The PCI slave acting as a master on the X-bus will insert wait states on write
cycles for data setup time. 0 = Disable; 1 = Enable.
Index 43h
PCI Arbitration Control 1 Register (R/W)
Default Value = 80h
7
BG
Bus Grant:
0 = Grants bus regardless of X-bus buffers.
1 = Grants bus only if X-bus buffers are empty.
6
5
RSVD
RME2
Reserved: Set to 1.
REQ2# Retry Mask Enable: Arbiter allows the REQ2# to be masked based on the master retry mask in
bits [2:1]: 0 = Disable; 1 = Enable.
4
3
RME1
RME0
MRM
REQ1# Retry Mask Enable: Arbiter allows the REQ1# to be masked based on the master retry mask in
bits [2:1]: 0 = Disable; 1 = Enable.
REQ0# Retry Mask Enable: Arbiter allows the REQ0# to be masked based on the master retry mask in
bits [2:1]: 0 = Disable; 1 = Enable.
2:1
Master Retry Mask: When a target issues a retry to a master, the arbiter can mask the request from the
retried master in order to allow other lower order masters to gain access to the PCI bus:
00 = No retry mask
01 = Mask for 16 PCI clocks
10 = Mask for 32 PCI clocks
11 = Mask for 64 PCI clocks
0
HXR
Hold X-bus on Retries: Arbiter holds the X-Bus X_HOLD for two additional clocks to see if the retried
master will request the bus again: 0 = Disable; 1 = Enable
(This may prevent retry thrashing in some cases.)
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