Integrated Functions (Continued)
4.6.8 PCI Cycles
The following sections and diagrams provide the func-
tional relationships for PCI cycles.
valid address and C/BE[3:0]# contains a valid bus com-
mand. The first data phase begins on clock 3. During the
data phase, AD[31:0] contains data and C/BE[3:0]# indi-
cate which byte lanes of AD[31:0] carry valid data. The
first data phase completes with zero delay cycles. How-
ever, the second phase is delayed one cycle because the
target was not ready so it deasserted TRDY# on clock 5.
The last data phase is delayed one cycle because the
master deasserted IRDY# on clock 7.
4.6.8.1 PCI Read Transaction
A PCI read transaction consists of an address phase and
one or more data phases. Data phases may consist of
wait cycles and a data transfer. Figure 4-18 illustrates a
PCI read transaction. In this example, there are three data
phases.
For additional information refer to Chapter 3.3.1, Read
Transaction, of the PCI Local Bus Specification, Revision
2.1.
The address phase begins on clock 2 when FRAME# is
asserted. During the address phase, AD[31:0] contains a
CLK
FRAME#
DATA-3
ADDR
DATA-2
DATA-1
AD
C/BE#
BUS CMD
BE#s
IRDY#
TRDY#
DEVSEL#
DATA
PHASE
ADDR
PHASE
DATA
PHASE
DATA
PHASE
BUS TRANSACTION
Figure 4-18. Basic Read Operation
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