4.0 Integrated Functions
The integrated functions in the Geode GXLV processor
are:
high chip count, small footprint designs. Performance deg-
radation in traditional UMA systems is reduced through
the use of National Semiconductor’s Display Compression
Technology (DCT) architecture.
•
•
•
•
Internal bus interface
SDRAM memory controller
Figure 4-1 shows the major functional blocks of the GXLV
processor and how the Internal Bus Interface Unit oper-
ates as the interface between the processor’s core units
and the integrated functions.
High-performance 2D graphics accelerator
Display controller with separate CRT and TFT data
paths
This section details how the integrated functions and
Internal Bus Interface Unit operate and their respective
registers.
•
PCI bridge
The design organizes the memory controller, graphics
pipeline and display controller into a Unified Memory
Architecture (UMA). UMA simplifies system designs and
significantly reduces overall system costs associated with
Write-Back
Cache Unit
Integer
FPU
MMU
Unit
C-Bus
Internal Bus Interface Unit
X-Bus
Graphics
Pipeline
Memory
Controller
Display
Controller
PCI
Controller
Integrated
Functions
PCI Bus
SDRAM Port
CS5530
(CRT/LCD TFT)
Figure 4-1. Internal Block Diagram
www.national.com
96
Revision 1.1
NSC [ National Semiconductor ]
