Processor Programming (Continued)
3.11 FLOATING POINT UNIT OPERATIONS
The GXLV processor contains an FPU that is x87 and
MMX instruction-set compatible and adheres to the IEEE-
754 standard. Because most applications that contain
FPU instructions intermix with integer instructions, the
GXLV processor’s FPU achieves high performance by
completing integer and FPU operations in parallel.
3.11.3 FPU Status Register
The FPU communicates status information and operation
results to the CPU through the FPU status register, whose
fields are detailed in Table 3-38. These fields include infor-
mation related to exception status, operation execution
status, register status, operand class, and comparison
results. This register is continuously accessible to the
CPU regardless of the state of the Control or Execution
Units.
3.11.1 FPU Register Set
The FPU provides the user eight data registers, a control
register, and a status register. The CPU also provides a
data register tag word that improves context switching and
stack performance by maintaining empty/non-empty sta-
tus for each of the eight data registers. Two additional,
registers contain pointers to (a) the memory location con-
taining the current instruction word and (b) the memory
location containing the operand associated with the cur-
rent instruction word (if any).
3.11.4 FPU Mode Control Register
The FPU Mode Control Register, shown in Table 3-38, is
used by the GXLV processor to specify the operating
mode of the FPU. The register fields include information
related to the rounding mode selected, the amount of pre-
cision to be used in the calculations, and the exception
conditions which should be reported to the GXLV proces-
sor using traps. The user controls precision, rounding,
and exception reporting by setting or clearing appropriate
bits.
3.11.2 FPU Tag Word Register
The FPU maintains a tag word register that is divided into
eight tag word fields. These fields assume one of four val-
ues depending on the contents of their associated data
registers: Valid (00), Zero (01), Special (10), and Empty
(11). Note: Denormal, Infinity, QNaN, SNaN and unsup-
ported formats are tagged as “Special”. Tag values are
maintained transparently by the CPU and are only avail-
able to the programmer indirectly through the FSTENV and
FSAVE instructions. The tag word with TAG fields for each
associated physical register, TAG(n), is shown in Table 3-
38.
www.national.com
94
Revision 1.1
NSC [ National Semiconductor ]
