Integrated Functions (Continued)
4.1.4 Scratchpad RAM
RAM is used by the graphics pipeline BLT buffers, and
National-supplied display drivers and virtualization soft-
ware. Table 4-3 describes the 2 KB, 3 KB, and 4 KB
scratchpad RAM organization used by National developed
software. The BLT buffers are programmed using
CPU_READ/CPU_WRITE instructions described in Sec-
tion 4.1.6 on page 102. If the graphics pipeline or National
software is used, and it is desirable to use scratchpad
RAM by software other than that supplied by National,
please contact your local National Semiconductor techni-
cal support representative.
To improve software performance for specific applications,
part of the L1 cache (2, 3, or 4 KB) can be programed to
operate as a scratchpad RAM. This scratchpad RAM
operates at L1 speed which can speed up time-critical
software operations. The scratchpad RAM is taken from
set 0 of the L1 cache. Setting aside this RAM makes the
L1 cache smaller by the scratchpad RAM size. The
scratchpad RAM size is controlled by bits in the GCR reg-
ister (Index B8h, bits[3:2]). See Table 4-1 on page 97.
The scratchpad RAM is usually memory mapped by BIOS
to the upper memory region defined by the GCR register
(Index B8h, bits [1:0]). Once enabled, the valid bits for the
scratchpad RAM will always be true and the scratchpad
RAM locations will never be flushed to external memory.
The scratchpad RAM serves as a general purpose high
speed RAM and as a BLT buffer for the graphics pipeline.
4.1.4.3 BLT Buffer
Address registers, BitBLT, have been added to the front
end of the L1 cache to enable the graphics pipeline to
directly access a portion of the scratchpad RAM as a BLT
buffer. Table 4-4 summarizes these registers. These regis-
ters do not have default values and must be initialized
before use. Table 4-5 gives the register/bit formats. A 16-
byte line buffer dedicated to the graphics pipeline BLT
operations has been added to minimize accesses to the
L1 cache.
4.1.4.1 Initialization of Scratchpad RAM
The scratchpad RAM must be initialized before the L1
cache is enabled. To initialize the scratchpad RAM after a
cold boot:
When the BLT operation begins, the graphics pipeline
generates a 32 bit data BLT request to the L1 cache. This
request goes through the BitBLT registers to produce an
1) Initialize the tags of the scratchpad RAM using the
test registers TR4 and TR5 as outlined in Section
3.3.2.4 “TLB Test Registers”. The tags are normally
programmed with an address value equivalent to
GX_BASE (GCR register).
address
into
the
scratchpad
RAM.
The
L1_BBx_POINTER register automatically increments
after each access. A BLT operation generates many
accesses to the BLT buffer to complete a BLT transfer. At
the end of the BLT operation the graphics pipeline gener-
ates a signal to reload the L1_BBx_POINTER register
with the L1_BBx_BASE register. This allows the BLT
buffer to be used over and over again with a minimum of
software overhead.
2) Enable the scratchpad RAM to the desired size (GCR
register). This action will also lock down the tags.
3) Enable the L1 cache. Section 3.3.2.1 “Control Regis-
ters”.
4.1.4.2 Scratchpad RAM Utilization
See Section 4.4 “Graphics Pipeline” on page 125 on pro-
gramming the graphics pipeline to generate a BLT.
Use of scratchpad RAM by applications and drivers must
be tightly controlled. To avoid conflicts, application soft-
ware and third-party drivers should generally avoid
accesses to the scratchpad RAM area. The scratchpad
Table 4-3. Scratchpad Organization
2 KB Configuration
3 KB Configuration
4 KB Configuration
Offset
Size
Offset
Size
Offset
Size
Description
GX_BASE + 0EE0h
GX_BASE + 0E60h
GX_BASE + 0800h
GX_BASE + 0B30h
288 bytes
128 bytes
816 bytes
816 bytes
GX_BASE + 0EE0h
GX_BASE + 0E60h
GX_BASE + 0400h
GX_BASE + 0930h
288 bytes
128 bytes
1328 bytes
1328 bytes
GX_BASE + 0EE0h
GX_BASE + 0E60h
GX_BASE + 0h
288 bytes
128 bytes
1840 bytes
1840 bytes
SMM scratchpad
Driver scratchpad
BLT Buffer 0
GX_BASE + 730h
BLT Buffer 1
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