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30036-23 参数 Datasheet PDF下载

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型号: 30036-23
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内容描述: 的Geode ™ GXLV处理器系列的低功耗X86集成解决方案 [Geode⑩ GXLV Processor Series Low Power Integrated x86 Solutions]
分类和应用:
文件页数/大小: 247 页 / 4117 K
品牌: NSC [ National Semiconductor ]
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Processor Programming (Continued)  
3.9.3 Privilege Level Transfers  
the correct descriptor type. Any violation of these descriptor  
usage rules causes a general protection fault.  
A tasks CPL can be changed only through intersegment  
control transfers using gates or task switches to a code  
segment with a different privilege level. Control transfers  
result from exception and interrupt servicing and from  
execution of the CALL, JMP, INT, IRET and RET instruc-  
tions.  
Any control transfer that changes the CPL within a task  
results in a change of stack. The initial values for the stack  
segment (SS) and stack pointer (ESP) for privilege levels  
0, 1, and 2 are stored in the TSS. During a JMP or CALL  
control transfer, the SS and ESP are loaded with the new  
stack pointer and the previous stack pointer is saved on  
the new stack. When returning to the original privilege  
level, the RET or IRET instruction restores the SS and  
ESP of the less-privileged stack.  
There are five types of control transfers that are summa-  
rized in Table 3-37. Control transfers can be made only  
when the operation causing the control transfer references  
Table 3-37. Descriptor Types Used for Control Transfer  
Descriptor  
Referenced  
Descriptor  
Table  
Type of Control Transfer  
Operation Types  
Intersegment within the same privilege  
level.  
JMP, CALL, RET, IRET*  
Code Segment  
GDT or LDT  
Intersegment to the same or a more  
privileged level. Interrupt within task  
(could change CPL level).  
CALL  
Gate Call  
GDT or LDT  
IDT  
Interrupt Instruction, Exception,  
External Interrupt  
Trap or Interrupt Gate  
Intersegment to a less privileged level  
(changes task CPL).  
RET, IRET*  
Code Segment  
GDT or LDT  
Task Switch via TSS  
CALL, JMP  
CALL, JMP  
Task State Segment  
Task Gate  
GDT  
Task Switch via Task Gate  
GDT or LDT  
IDT  
IRET**, Interrupt Instruction,  
Exception, External Interrupt  
Task Gate  
Note: *NT = 0 (Nested Task bit in EFLAGS, bit 14)  
**NT =1 (Nested Task bit in EFLAGS, bit 14)  
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