Processor Programming (Continued)
3.9.3.1 Gates
The paging hardware allows multiple V86 tasks to run
concurrently, and provides protection and operating sys-
tem isolation. The paging hardware must be enabled to
run multiple V86 tasks or to relocate the address space of
a V86 task to physical address space other than 0.
Gate descriptors described in Section “Gate Descriptors”
on page 74, provide protection for privilege transfers
among executable segments. Gates are used to transition
to routines of the same or a more privileged level. Call
gates, interrupt gates and trap gates are used for privilege
transfers within a task. Task gates are used to transfer
between tasks.
3.10.2 Protection
All V86 tasks operate with the least amount of privilege
(level 3) and are subject to all CPU protected mode protec-
tion checks. As a result, any attempt to execute a privi-
leged instruction within a V86 task results in a general
protection fault.
Gates conform to the standard rules of privilege. In other
words, gates can be accessed by a task if the effective
privilege level (EPL) is the same or more privileged than
the gate descriptor’s privilege level (DPL).
In V86 mode, a slightly different set of instructions are
sensitive to the I/O privilege level (IOPL) than in protected
mode. These instructions are: CLI, INT n, IRET, POPF,
PUSHF, and STI. The INT3, INTO and BOUND variations
of the INT instruction are not IOPL sensitive.
3.9.4 Initialization and Transition to Protected Mode
The GXLV processor core switches to real mode immedi-
ately after RESET. While operating in real mode, the sys-
tem tables and registers should be initialized. The GDTR
and IDTR must point to a valid GDT and IDT, respectively. The
size of the IDT should be at least 256 bytes, and the GDT
must contain descriptors that describe the initial code and
data segments.
3.10.3 Interrupt Handling
To fully support the emulation of an 8086-type machine,
interrupts in V86 mode are handled as follows. When an
interrupt or exception is serviced in V86 mode, program
execution transfers to the interrupt service routine at privi-
lege level 0 (i.e., transition from V86 to protected mode
occurs). The VM bit in the EFLAGS register (bit 17) is
cleared. The protected mode interrupt service routine
then determines if the interrupt came from a protected
mode or V86 application by examining the VM bit in the
EFLAGS image stored on the stack. The interrupt service
routine may then choose to allow the 8086 operating sys-
tem to handle the interrupt or may emulate the function of
the interrupt handler. Following completion of the interrupt
service routine, an IRET instruction restores the EFLAGS
register (restores VM = 1) and segment selectors and
control returns to the interrupted V86 task.
The processor can be placed in protected mode by setting
the PE bit (CR0 register bit 0). After enabling protected
mode, the CS register should be loaded and the instruc-
tion decode queue should be flushed by executing an
intersegment JMP. Finally, all data segment registers
should be initialized with appropriate selector values.
3.10 VIRTUAL 8086 MODE
Both real mode and virtual 8086 (V86) modes are sup-
ported by the GXLV processor, allowing execution of 8086
application programs and 8086 operating systems. V86
mode allows the execution of 8086-type applications, yet
still permits use of the paging and protection mechanisms.
V86 tasks run at privilege level 3. Before entry, all seg-
ment limits must be set to FFFFh (64K) as in real mode.
3.10.4 Entering and Leaving Virtual 8086 Mode
V86 mode is entered from protected mode by either exe-
cuting an IRET instruction at CPL = 0 or by task switching.
If an IRET is used, the stack must contain an EFLAGS
image with VM = 1. If a task switch is used, the TSS must
contain an EFLAGS image containing a 1 in the VM bit
position. The POPF instruction cannot be used to enter
V86 mode since the state of the VM bit is not affected.
V86 mode can only be exited as the result of an interrupt
or exception. The transition out must use a 32-bit trap or
interrupt gate that must point to a non-conforming privi-
lege level 0 segment (DPL = 0), or a 32-bit TSS. These
restrictions are required to permit the trap handler to IRET
back to the V86 program.
3.10.1 Memory Addressing
While in V86 mode, segment registers are used in an
identical fashion to real mode. The contents of the Seg-
ment register are multiplied by 16 and added to the offset
to form the Segment Base Linear Address. The GXLV pro-
cessor permits the operating system to select which pro-
grams use the V86 address mechanism and which
programs use protected mode addressing for each task.
The GXLV processor also permits the use of paging when
operating in V86 mode. Using paging, the 1 MB address
space of the V86 task can be mapped to any region in the
4 GB linear address space.
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