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30036-23 参数 Datasheet PDF下载

30036-23图片预览
型号: 30036-23
PDF下载: 下载PDF文件 查看货源
内容描述: 的Geode ™ GXLV处理器系列的低功耗X86集成解决方案 [Geode⑩ GXLV Processor Series Low Power Integrated x86 Solutions]
分类和应用:
文件页数/大小: 247 页 / 4117 K
品牌: NSC [ National Semiconductor ]
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Processor Programming (Continued)  
3.3.2.2 Configuration Registers  
Each data transfer through I/O Port 23h must be preceded  
by a register index selection through I/O Port 22h; other-  
wise, subsequent I/O Port 23h operations are directed off-  
chip and produce external I/O cycles.  
The Configuration Registers listed in Table 3-9 are CPU  
registers and are selected by register index numbers. The  
registers are accessed through I/O memory locations 22h  
and 23h. Registers are selected for access by writing an  
index number to I/O Port 22h using an OUT instruction  
prior to transferring data through I/O Port 23h. This opera-  
tion must be atomic. The CLI instruction must be executed  
prior to accessing any of these registers.  
If MAPEN, bit 4 of CCR3 (Index C3h[4]) = 0, external I/O  
cycles occur if the register index number is outside the  
range C0h-CFh, FEh, and FFh. The MAPEN bit should  
remain 0 during normal operation to allow system regis-  
ters located at I/O Port 22h to be accessed (see Table 3-  
11 on page 52).  
Table 3-9. Configuration Register Summary  
Access Default  
Reference  
Index  
Type  
Name  
Controlled By*  
Value  
(Bit Formats)  
C1h  
C2h  
C3h  
E8h  
EBh  
20h  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
RO  
CCR1 — Configuration Control 1  
CCR2 — Configuration Control 2  
CCR3 — Configuration Control 3  
CCR4 — Configuration Control 4  
CCR7 — Configuration Control 7  
PCR — Performance Control  
SMHR0 — SMM Header Address 0  
SMHR1 — SMM Header Address 1  
SMHR2 — SMM Header Address 2  
SMHR3 — SMM Header Address 3  
GCR — Graphics Control Register  
VGACTL — VGA Control Register  
VGAM0 — VGA Mask Register  
SMAR0 — SMM Address 0  
SMI_LOCK  
--  
00h  
00h  
00h  
85h  
00h  
07h  
xxh  
xxh  
xxh  
xxh  
00h  
00h  
00h  
00h  
00h  
00h  
4xh  
xxh  
Table 3-11 on page 52  
Table 3-11 on page 52  
Table 3-11 on page 52  
Table 3-11 on page 53  
Table 3-11 on page 53  
Table 3-11 on page 53  
Table 3-11 on page 54  
Table 3-11 on page 54  
Table 3-11 on page 54  
Table 3-11 on page 54  
Table 4-1 on page 97  
Table 4-37 on page 163  
Table 4-37 on page 163  
Table 3-11 on page 54  
Table 3-11 on page 54  
Table 3-11 on page 54  
Table 3-11 on page 54  
Table 3-11 on page 54  
SMI_LOCK  
MAPEN  
--  
MAPEN  
MAPEN  
MAPEN  
MAPEN  
MAPEN  
MAPEN  
--  
B0h  
B1h  
B2h  
B3h  
B8h  
B9h  
BAh-BDh  
CDh  
CEh  
CFh  
FEh  
FFh  
--  
SMI_LOCK  
SMI_LOCK  
SMI_LOCK  
--  
SMAR1 — SMM Address 1  
SMAR2 — SMM Address 2  
DIR0 — Device ID 0  
RO  
DIR1 — Device ID 1  
--  
Note: *MAPEN = Index C3h[4] (CCR3) and SMI_LOCK = Index C3h[0] (CCR3).  
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