Processor Programming (Continued)
3.3.2 System Register Set
Table 3-5. System Register Set
The System Register Set, shown in Table 3-5, consists of
registers not generally used by application programmers.
These registers are typically employed by system level
programmers who generate operating systems and mem-
ory management programs. Associated with the System
Register Set are certain tables and segments which are
listed in Table 3-5.
Width
(Bits)
Group
Control
Registers
Name
CR0
Function
System Control
Register
32
32
32
CR2
CR3
CR4
Page Fault Linear
Address Register
Page Directory Base
Register
The Control Registers control certain aspects of the
GXLV processor such as paging, coprocessor functions,
and segment protection.
Time Stamp Counter
32
8
Configuration CCRn
Registers
Configuration Control
Registers
The Configuration Registers are used to define the
GXLV CPU setup including cache management.
Debug
Registers
DR0
DR1
DR2
DR3
Linear Breakpoint
Address 0
32
32
32
32
The Debug Registers provide debugging facilities for the
GXLV processor and enable the use of data access
breakpoints and code execution breakpoints.
Linear Breakpoint
Address 1
Linear Breakpoint
Address 2
The Test Registers provide a mechanism to test the con-
tents of both the on-chip 16 KB cache and the Translation
Lookaside Buffer (TLB).
Linear Breakpoint
Address 3
DR6
DR7
TR3
TR4
TR5
TR6
TR7
GDT
IDT
Breakpoint Status
Breakpoint Control
Cache Test
32
32
32
32
32
32
32
32
32
The Descriptor Table Register hold descriptors that
manage memory segments and tables, interrupts and
task switching. The tables are defined by corresponding
registers.
Test
Registers
Cache Test
The two Task State Segment Tables defined by TSS reg-
ister are used to save and load the computer state when
switching tasks.
Cache Test
TLB Test Control
TLB Test Data
The ID Registers allow BIOS and other software to iden-
tify the specific CPU and stepping.
Descriptor
Tables
General Descriptor Table
Interrupt Descriptor
Table
System Management Mode (SMM) control information is
stored in the SMM Registers.
LDT
Local Descriptor Table
GDT Register
16
32
32
16
16
Descriptor
Table
Registers
GDTR
IDTR
LDTR
TSS
Table 3-5 lists the system register sets along with their
size and function.
IDT Register
LDT Register
Task State
Segment and
Registers
Task State Segment
Table
TR
TSS Register Setup
16
8
ID
DIRn
Device Identification
Registers
Registers
SMM
Registers
SMARn
SMHRn
SMM Address Region
Registers
8
SMM Header Addresses
8
8
Performance PCR0
Registers
Performance Control
Register
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