Processor Programming (Continued)
Table 3-10. Configuration Register Map
Register
(Index)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Registers
CCR1 (C1h)
RSVD
SMAC
LOCK_NW
RSVD
USE_SMI
RSVD
CCR2 (C2h)
CCR3 (C3h)
USE_SUSP
LSS_34
RSVD
WT1
SUSP_HLT
RSVD
LSS_23
LSS_12
MAPEN
SUSP_SMM
_EN
NMI_EN
IORT1
RSVD
SMI_LOCK
CCR4 (E8h)
CPUID
LSSER
SMI_NEST FPU_FAST_
EN
DTE_EN
MEM_BYP
IORT2
NMI
IORT0
CCR7 (EBh)
PCR (20h)
RSVD
EMMX
RSVD
SMM Base Header Address Registers
SMHR0 (B0h)
SMHR1 (B1h)
SMHR2 (B2h)
SMHR3 (B3h)
SMAR0 (CDh)
SMAR1 (CEh)
SMAR2 (CFh)
A7
A6
A5
A4
A3
A11
A2
A10
A1
A9
A0
A8
A15
A23
A31
A31
A23
A15
A14
A22
A30
A30
A22
A14
A13
A21
A29
A29
A21
A13
A12
A20
A28
A28
A20
A12
A19
A18
A17
A26
A25
A17
SIZE1
A16
A24
A24
A16
SIZE0
A27
A26
A27
A26
A19
A18
SIZE3
SIZE2
Device ID Registers
DIR0 (FEh)
DIR1 (FFh)
DID3
SID3
DID2
SID2
DID1
SID1
DID0
SID0
MULT3
RID3
MULT2
RID2
MULT1
RID1
MULT0
RID0
Graphics/VGA Related Registers
GCR (B8h)
RSVD
Scratchpad Size
Base Address Code
VGACTL (B9h)
RSVD
Enable SMI Enable SMI Enable SMI
for VGA
memory
B8000h to
BFFFFh
for VGA
memory
B0000h to
B7FFFh
for VGA
memory
A0000h to
AFFFFh
VGAM0 (BAh)
VGAM1 (BBh)
VGAM2 (BCh)
VGAM3 (BDh)
VGA Mask Register Bits [7:0]
VGA Mask Register Bits [15:8]
VGA Mask Register Bits [23:16]
VGA Mask Register Bits [31:24]
Revision 1.1
51
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