Processor Programming (Continued)
Table 3-11. Configuration Registers (Continued)
Bit
Name
Description
SMHR — SMM Header Address Register (R/W)
Index B0h, B1h, B2h, B3h
Default Value = xxh
Index
SMHR Bits
SMM Header Address Bits [31:0]: SMHR address bits [31:0] contain the physical base address for
the SMM header space. For example, bits [31:24] correspond with Index B3h. Refer to Section 3.7.3
“SMM Configuration Registers” on page 85 for more information.
B3h
B2h
B1h
B0h
A[31:24]
A[23:16]
A[15:12]
A[7:0]
Note: MAPEN (CCR3[4]) must = 1 to read or write to this register.
Index CDh, CEh, CFh SMAR — SMM Address Region/Size Register (R/W)
Default Value = 00h
Index
SMAR Bits
SMM Address Region Bits [A31:A12]: SMAR address bits [31:12] contain the base address for the
SMM region. For example, bits [31:24] correspond with index CDh. Refer to Section 3.7.3 “SMM Con-
figuration Registers” on page 85 for more information.
CDh
CEh
CFh[7:4]
A[31:24]
A[23:16]
A[15:12]
CFh[3:0]
SIZE[3:0]
SMM Region Size Bits [3:0]: SIZE address bits contain the size code for the SMM region. During
access the lower 4-bits of Port 23h hold SIZE[3:0]. Index CFh allows simultaneous access to SMAR
address regions bits A[15:12] (see above) and size code bits SIZE[3:0].
0000 = SMM Disabled
0001 = 4 KB
0010 = 8 KB
0100 = 32 KB
0101 = 64 KB
0110 = 128 KB
0111 = 256 KB
1000 = 512 KB
1001 = 1 MB
1010 = 2 MB
1011 = 4 MB
1100 = 8 MB
1101 = 16 MB
1110 = 32 MB
1111 = 4 KB (same as 0001)
0011 = 16 KB
Notes: 1. SMI_LOCK (CCR3[0]) must = 0, or the CPU must be in SMI mode, to write these registers/bits.
2. Refer to Section 3.7.3 “SMM Configuration Registers” on page 85 for more information.
Index FEh
DIR0 — Device Identification Register 0 (RO)
Default Value = 4xh
7:4
3:0
DID[3:0]
Device ID (Read Only): Identifies device as GXLV processor.
MULT[3:0]
Core Multiplier (Read Only): Identifies the core multiplier set by the CLKMODE[2:0] pins (see signal
descriptions page 31)
MULT[3:0]:
0000 = SYSCLK multiplied by 4 (Test mode only)
0001 = SYSCLK multiplied by 10
0010 = SYSCLK multiplied by 4
0011 = SYSCLK multiplied by 6
0100 = SYSCLK multiplied by 9
0101 = SYSCLK multiplied by 5
0110 = SYSCLK multiplied by 7
0111 = SYSCLK multiplied by 8
1xxx = Reserved
Index FFh
DIR1 — Device Identification Register 1 (RO)
Default Value = xxh
7:0
DIR1
Device Identification Revision (Read Only): DIR1 indicates device revision number.
If DIR1 is 6xh = GXLV processor.
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