欢迎访问ic37.com |
会员登录 免费注册
发布采购

30036-23 参数 Datasheet PDF下载

30036-23图片预览
型号: 30036-23
PDF下载: 下载PDF文件 查看货源
内容描述: 的Geode ™ GXLV处理器系列的低功耗X86集成解决方案 [Geode⑩ GXLV Processor Series Low Power Integrated x86 Solutions]
分类和应用:
文件页数/大小: 247 页 / 4117 K
品牌: NSC [ National Semiconductor ]
 浏览型号30036-23的Datasheet PDF文件第44页浏览型号30036-23的Datasheet PDF文件第45页浏览型号30036-23的Datasheet PDF文件第46页浏览型号30036-23的Datasheet PDF文件第47页浏览型号30036-23的Datasheet PDF文件第49页浏览型号30036-23的Datasheet PDF文件第50页浏览型号30036-23的Datasheet PDF文件第51页浏览型号30036-23的Datasheet PDF文件第52页  
Processor Programming (Continued)  
3.3.2.1 Control Registers  
The CD bit (Cache Disable, bit 30) in CR0 globally con-  
trols the operating mode of the L1 cache. LCD and LWT,  
Local Cache Disable and Local Write-through bits in the  
Translation Lookaside Buffer, control the mode on a page-  
by-page basis. Additionally, memory configuration control  
can specify certain memory regions as non-cacheable.  
A map of the Control Registers (CR0, CR1, CR2, CR3,  
and CR4) is shown in Table 3-6 and the bit definitions are  
given in Table 3-7. (These registers should not be confused  
with the CRRn registers.) CR0 contains system control bits  
which configure operating modes and indicate the general  
state of the CPU. The lower 16 bits of CR0 are referred to  
as the Machine Status Word (MSW).  
If the cache is disabled, no further cache line fills occur.  
However, data already present in the cache continues to  
be used. For the cache to be completely disabled, the  
cache must be invalidated with a WBINVD instruction  
after the cache has been disabled.  
When operating in real mode, any program can read and  
write the control registers. In protected mode, however,  
only privilege level 0 (most-privileged) programs can read  
and write these registers.  
Write-back caching improves performance by relieving  
congestion on slower external buses. With four dirty bits,  
L1 Cache Controller  
the cache marks dirty locations on  
a double-word  
The GXLV processor contains an on-board 16 KB unified  
data/instruction write-back L1 cache. With the memory  
controller on-board, the L1 cache requires no external  
logic to maintain coherency. All DMA cycles automatically  
snoop the L1 cache.  
(DWORD) basis. This further reduces the number of  
DWORD write operations needed during a replacement or  
flush operation.  
The GXLV processor will cache SMM regions, reducing  
system management overhead to allow for hardware  
emulation such as VGA.  
Table 3-6. Control Registers Map  
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  
9
8
7
6
5
4
3
2
1
0
CR4 Register  
Control Register 4 (R/W)  
RSVD  
T
S
C
RSVD  
CR3 Register  
CR2 Register  
CR1 Register  
CR0 Register  
Control Register 3 (R/W)  
PDBR (Page Directory Base Register)  
RSVD  
0
0
RSVD  
Control Register 2 (R/W)  
PFLA (Page Fault Linear Address)  
Control Register 1 (R/W)  
RSVD  
Control Register 0 (R/W)  
P
G
C
D
N
W
RSVD  
A
M
R
S
V
D
W
P
RSVD  
N
E
R
S
V
D
T
S
E
M
M
P
P
E
Machine Status Word (MSW)  
Table 3-7. CR4-CR0 Bit Definitions  
Bit  
Name Description  
CR4 Register  
Control Register 4 (R/W)  
31:3  
2
RSVD Reserved: Set to 0 (always returns 0 when read).  
TSC  
Time Stamp Counter Instruction:  
If = 1 RDTSC instruction enabled for CPL = 0 only; reset state.  
If = 0 RDTSC instruction enabled for all CPL states.  
1:0  
RSVD Reserved: Set to 0 (always returns 0 when read).  
Control Register 3 (R/W)  
CR3 Register  
31:12  
11:0  
PDBR Page Directory Base Register: Identifies page directory base address on a 4 KB page boundary.  
RSVD Reserved: Set to 0.  
www.national.com  
48  
Revision 1.1