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30036-23 参数 Datasheet PDF下载

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型号: 30036-23
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内容描述: 的Geode ™ GXLV处理器系列的低功耗X86集成解决方案 [Geode⑩ GXLV Processor Series Low Power Integrated x86 Solutions]
分类和应用:
文件页数/大小: 247 页 / 4117 K
品牌: NSC [ National Semiconductor ]
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Processor Programming (Continued)  
3.3.1.4 EFLAGS Register  
The EFLAGS Register contains status information and  
controls certain operations on the GXLV processor. The  
lower 16 bits of this register are referred to as the  
EFLAGS register that is used when executing 8086 or  
80286 code. Table 3-4 gives the bit formats for the  
EFLAGS Register  
Table 3-4. EFLAGS Register  
Bit  
Name  
Flag Type  
Description  
Reserved: Set to 0.  
31:22  
21  
RSVD  
ID  
--  
System  
Identification Bit: The ability to set and clear this bit indicates that the CPUID instruction is sup-  
ported. The ID can be modified only if the CPUID bit in CCR4 (Index E8h[7]) is set.  
20:19  
18  
RSVD  
AC  
--  
Reserved: Set to 0.  
System  
Alignment Check Enable: In conjunction with the AM flag (bit 18) in CR0, the AC flag deter-  
mines whether or not misaligned accesses to memory cause a fault. If AC is set, alignment faults  
are enabled.  
17  
16  
VM  
RF  
System  
Debug  
Virtual 8086 Mode: If set while in protected mode, the processor switches to virtual 8086 opera-  
tion handling segment loads as the 8086 does, but generating exception 13 faults on privileged  
opcodes. The VM bit can be set by the IRET instruction (if current privilege level is 0) or by task  
switches at any privilege level.  
Resume Flag: Used in conjunction with debug register breakpoints. RF is checked at instruction  
boundaries before breakpoint exception processing. If set, any debug fault is ignored on the next  
instruction.  
15  
14  
RSVD  
NT  
--  
Reserved: Set to 0.  
System  
Nested Task: While executing in protected mode, NT indicates that the execution of the current  
task is nested within another task.  
13:12  
IOPL  
System  
Arithmetic  
Control  
I/O Privilege Level: While executing in protected mode, IOPL indicates the maximum current  
privilege level (CPL) permitted to execute I/O instructions without generating an exception 13  
fault or consulting the I/O permission bit map. IOPL also indicates the maximum CPL allowing  
alteration of the IF bit when new values are popped into the EFLAGS register.  
11  
OF  
Overflow Flag: Set if the operation resulted in a carry or borrow into the sign bit of the result but  
did not result in a carry or borrow out of the high-order bit. Also set if the operation resulted in a  
carry or borrow out of the high-order bit but did not result in a carry or borrow into the sign bit of  
the result.  
10  
DF  
Direction Flag: When cleared, DF causes string instructions to auto-increment (default) the  
appropriate index registers (ESI and/or EDI). Setting DF causes auto-decrement of the index  
registers to occur.  
9
8
IF  
System  
Debug  
Interrupt Enable Flag: When set, maskable interrupts (INTR input pin) are acknowledged and  
serviced by the CPU.  
TF  
Trap Enable Flag: Once set, a single-step interrupt occurs after the next instruction completes  
execution. TF is cleared by the single-step interrupt.  
7
6
5
4
SF  
ZF  
Arithmetic  
Arithmetic  
--  
Sign Flag: Set equal to high-order bit of result (0 indicates positive, 1 indicates negative).  
Zero Flag: Set if result is zero; cleared otherwise.  
Reserved: Set to 0.  
RSVD  
AF  
Arithmetic  
Auxiliary Carry Flag: Set when a carry out of (addition) or borrow into (subtraction) bit position 3  
of the result occurs; cleared otherwise.  
3
2
RSVD  
PF  
--  
Reserved: Set to 0.  
Arithmetic  
Parity Flag: Set when the low-order 8 bits of the result contain an even number of ones; other-  
wise PF is cleared.  
1
0
RSVD  
CF  
Reserved: Set to 1.  
Arithmetic  
Carry Flag: Set when a carry out of (addition) or borrow into (subtraction) the most significant bit  
of the result occurs; cleared otherwise.  
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Revision 1.1