Fig. 5-7 LCD Controller/Driver Block Diagram
4
8
4
4
8
Port Mode
Register
Group A
Port 3
Output
Latch
1FFH
1FEH
1E9H
1E8H
1E0H
Display
Control
Register
Display Mode
Register
Display Data
Memory
3
3
2
1
0
0
3
3
2
1
0
0
3
3
2
1
0
0
3
3
2
1
0
0
3
3
2
1
0
0
1
0
1
0
2
1
2
1
2
1
2
1
2
1
Timing
Controller
f
LCD
Multi-
plexer
µ
Selector
LCD Driver Voltage
Control
Segment Driver
S24/PB0
Common Driver
S31/PB7
S30/PB6
S23
S0 COM3 COM2 COM1 COM0LC2 VVLC1
VLC0 P31/ P30/
SYNC LCDCL