Fig. 5-5 Timer/Event Counter Block Diagram
Internal Bus
*1
8
SET1
8
8
TM0
TMOD0
TOE0
PORT2.0
Bit 2 of PGMB
Port 2
TO
Enable
Flag
P20
Output
Latch
Modulo Register (8)
TM06 TM05 TM04 TM03 TM02
Input/
Output
Mode
To Serial
Interface
8
PORT1.3
Match
TOUT
F/F
Comparator (8)
P20/PTO0
Output
Buffer
Input Buffer
8
Reset
P13/TI0
T0
INTT0
IRQT0
Set Signal
Count Register (8)
Clear
*2
From Clock
Generator
MPX
CP
µ
Timer Operation Start
RESET
IRQT0
Clear Signal
*
1
2
SET1: Instruction execution
For detail, see Fig. 5-1.