Fig. 5-6 Serial Interface Block Diagram
Internal Bus
8
Bit
Test
Bit Manipulation
(8)
Bit Test
8/4
8
8
Slave Address Register (SVA)
Addres Comparator
Shift Register (SIO)
CSIM
SBIC
Match
Signal
(8)
RELT
CMDT
P03/SI/SB1
P02/SO/SB0
SO
Latch
SET CLR
D
Q
(8)
Busy/
Acknowledge
Output Circuit
RELD
CMDD
ACKD
Bus Release/
Command/
Acknowledge
Detection Circuit
P01/SCK
INTCSI
Serial Clock
Counter
INTCSI Control
Circuit
IRQCSI
µ
Set Signal
/23
/24
/26
P01
Output
Latch
f
f
f
X
X
X
Serial
Clock
Slector
Serial Clock
Control Circuit
TOUT F/F
(From Timer/
Event Counter)
External
SCK
NEC [ NEC ]
