CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION
4.5 FPGA Top Pin Configuration
The connection diagram of the PCI host bridge macro pins in an FPGA is shown below.
4.5.1 Internal connection diagram of external bus interface
FPGA top
VBRESETZ
RESET
CS6
PCI host
bridge macro
I_SRST_B
CS6
I_CPU_CS0_B
Address
I_CPU_CS1_B
decoder
I_CPU_CS2_B
RA0
A0
I_SRST_B
I_CPU_ADR1 to I_CPU_ADR19
RA1 to RA25
A1 to A25
O_SD_ADR1 to O_SD_ADR25
I_CPU_DATA0 to I_CPU_DATA31
I_SD_DATA0 to I_SD_DATA31
O_CPU_DATA0 to O_CPU_DATA31
O_SD_DATA0 to O_SD_DATA31
EN_CPU_DATA
RD0 to RD31
D0 to D31
Selector
Selector
EN_SD_DATA0, EN_SD_DATA1
BENZ0 to BENZ3
I_CPU_BE_B0 to I_CPU_BE_B3
DQM0 to DQM3 xxBE/xxDQM
O_SD_DQM_B0 to O_SD_DQM_B3
I_CPU_WE_B
O_SD_WR_B
WRZ
WE/WR
RDZ
RD
WAIT
I_CPU_OE_B
O_CPU_WAIT_B
O_PCIHOST_INT
O_HOLDRQ_B
I_HOLDACK_B
O_SD_CKE
WAITZ
INT0
INTP10
HLDRQ
HLDAK
SDCKE
HLDRQZ
HLDAKZ
SDCKE
SDCSZ
CS3
O_SD_CS_B
O_SD_RAS_B
O_SD_CAS_B
SDRASZ
SDRAS
SDCASZ
SDCLK
SDCAS
BUSCLK
I_SDCLK
EN_SD_CTL
I/O buffer
61
Application Note U17121EJ1V1AN
NEC [ NEC ]
