CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION
4.3 Reference Diagram for FPGA Top Connection
The reference diagram for connecting the PCI host bridge macro with the FPGA top layer is shown below.
FPGA top
PCI host bridge macro
VBRESETZ
CSZ6
I_SRST_B
I_PCLK
PCLK
I_CPU_CS0_B
I_CPU_CS1_B
I_CPU_CS2_B
O_PCIRST_B
PCIRST
Address
decoder
RA21 to
RA25
I_AD0 to I_AD31
O_AD0 to O_AD31
EN_AD
AD0 to
AD31
RA0
I_CPU_ADR0
I_CPU_ADR1 to I_CPU_ADR19
I_CBE0 to I_CBE3
CBE0 to
CBE3
RA1 to RA25
O_SD_ADR1 to O_SD_ADR25 O_CBE0 to O_CBE3
EN_CBE
I_CPU_DATA0 to I_CPU_DATA31
I_FRAME_B
I_SD_DATA0 to I_SD_DATA31
O_FRAME_B
FRAME
IRDY
RD0 to RD31
O_CPU_DATA0 to O_CPU_DATA31
Selector
EN_FRAME
O_SD_DATA0 to O_SD_DATA31
I_IRDY_B
EN_CPU_DATA
O_IRDY_B
EN_SD_DATA0, EN_SD_DATA1
EN_IRDY
BENZ0 to
BENZ3
I_CPU_BE_B0 to I_CPU_BE_B3
I_DEVSEL_B
WRZ0
RDZ
I_CPU_WE_B
O_DEVSEL_B
DEVSEL
TRDY
STOP
PAR
I_CPU_OE_B
EN_DEVSEL
WAITZ
O_CPU_WAIT_B
I_TRDY_B
O_TRDY_B
HLDRQZ
HLDAKZ
SDCLK
O_HOLDREQ_B
EN_TRDY
I_HOLDACK_B
I_STOP_B
I_SDCLK
O_STOP_B
DQM0 to
DQM3
EN_STOP
O_SD_DQM_B0 to O_SD_DQM_B3
I_PAR
SDCKE
SDCS
O_SD_CKE
O_PAR
EN_PAR
O_SD_CS_B
I_PERR_B
SDRASZ
SDCASZ
SDWEZ
O_SD_RAS_B
O_SD_CAS_B
O_PERR_B
EN_PERR
PERR
SERR
I_SERR_B
O_SD_WR_B
EN_SD_CTL
EN_SDCLK
I_REQ_B1
I_REQ_B2
REQ1
REQ2
Open
I_REQ_B3 to I_REQ_B7
Internal H
fixed input
O_GNT_B1
O_GNT_B2
GNT1
GNT2
O_GNT_B3 to O_GNT_B7
Open
O_PCIHOST_IN
INT0
INT1
INT2
INTA
INTB
58
Application Note U17121EJ1V1AN
NEC [ NEC ]
