µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
(c) Write timing (high-speed page DRAM access, normal access: off-page) (1/2)
Parameter
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
Row address setup time
Symbol
<24>
Condition
MIN.
10
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
tSWK
tHKW
tASR
tRAH
tASC
tCAH
tRC
<25>
<56>
<57>
<58>
<59>
<60>
2
(0.5 + wRP) T – 10
(0.5 + wRH) T – 10
0.5T – 10
Row address hold time
Column address setup time
Column address hold time
Read/write cycle time
(1.5 + wDA + w) T – 10
(3 + wRP + wRH + wDA + w)
T – 10
RAS precharge time
RAS pulse time
<61>
<62>
tRP
(0.5 + wRP) T – 5
ns
ns
tRAS
(2.5 + wRH + wDA + w)
T – 10
RAS hold time
<63>
<64>
<65>
<66>
<67>
tRSH
tRAL
tCAS
tCRP
tCSH
(1.5 + wDA + w) T – 10
(2 + wDA + w) T – 10
(1 + wDA + w) T – 10
(1 + wRH) T – 10
ns
ns
ns
ns
ns
Column address read time (from RAS
CAS pulse width
↑
)
CAS-RAS precharge time
CAS hold time
(2 + wRH + wDA + w)
T – 10
CAS precharge time
<71>
<76>
<77>
<84>
tCPN
tRAD
tRCD
tWCS
(2 + wRP + wRH) T – 5
(0.5 + wRH) T – 10
(1 + wRH) T – 10
ns
ns
ns
ns
RAS column address delay time
RAS-CAS delay time
WE setup time (to CAS ↓)
(1 + wRP + wRH )
T – 10
WE hold time (from CAS ↓)
Data setup time (to CAS ↓)
Data hold time (from CAS ↓)
<85>
<86>
<87>
tWCH
tDS
(1 + wDA + w) T – 10
ns
ns
ns
(1.5 + wRP + wRH
)
T – 10
tDH
(1.5 + wDA + w) T – 10
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
98
Preliminary Data Sheet U14168EJ2V0DS00
NEC [ NEC ]
