µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
(d) Write timing (high-speed page DRAM access: on-page) (2/2)
TCPW
TO1
TDAW
TO2
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
<58>
<59>
<63>
Column address
<64>
<83>
<81>
<65>
UCAS (Output)
LCAS (Output)
<89>
<88>
OE (Output)
WE (Output)
<84>
<85>
<92>
<91>
<90>
<86>
<87>
D0 to D15 (I/O)
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the CPCxx bit of the DRCn register (TCPW ): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
101
Preliminary Data Sheet U14168EJ2V0DS00
NEC [ NEC ]
