µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
(d) Write timing (high-speed page DRAM access: on-page) (1/2)
Parameter
Symbol
<58>
Condition
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
Column address setup time
Column address hold time
RAS hold time
tASC
tCAH
tRSH
tRAL
tCAS
tCP
(0.5 + wCP) T – 10
(1.5 + wDA) T – 10
(1.5 + wDA) T – 10
(2 + wCP + wDA) T – 10
(1 + wDA) T – 10
(1 + wCP) T – 5
<59>
<63>
<64>
<65>
<81>
<83>
Column address read time (from RAS
CAS pulse width
↑
)
CAS precharge time
RAS hold time for CAS precharge
tRHCP
(2.5 + wCP + wDA
)
T – 10
WE setup time (to CAS ↓)
WE hold time (from CAS ↓)
Data setup time (to CAS ↓)
Data hold time (from CAS ↓)
WE read time (from RAS ↑)
WE read time (from CAS ↑)
Data setup time (to WE ↓)
Data hold time (from WE ↓)
WE pulse width
<84>
<85>
<86>
<87>
<88>
<89>
<90>
<91>
<92>
tWCS
tWCH
tDS
wCP ≥ 1
wCPT – 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1 + wDA) T – 10
(0.5 + wCP) T – 10
(1.5 + wDA) T – 10
(1.5 + wDA) T – 10
(1 + wDA) T – 10
0.5T – 10
tDH
tRWL
tCWL
tDSWE
tDHWE
tWP
wCP = 0
wCP = 0
wCP = 0
wCP = 0
wCP = 0
(1.5 + wDA) T – 10
(1 + wDA) T – 10
Remarks 1. T = tCYK
2. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
100
Preliminary Data Sheet U14168EJ2V0DS00
NEC [ NEC ]
