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UPD703100AGJ-40-8EU 参数 Datasheet PDF下载

UPD703100AGJ-40-8EU图片预览
型号: UPD703100AGJ-40-8EU
PDF下载: 下载PDF文件 查看货源
内容描述: V850E / MS1TM 16分之32位单芯片微控制器 [V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 132 页 / 1155 K
品牌: NEC [ NEC ]
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µPD703100A-33, 703100A-40, 703101A-33, 703102A-33  
Data Hold Characteristics(TA = –40 to +70°C ... µPD703100A-40,  
TA = –40 to +85°C ... µPD703100A-33, µPD703101A-33, µPD703102A-33)  
Parameter  
Data hold voltage  
Symbol  
VDDDR  
IDDDR  
Condition  
STOP mode, VDD = VDDDR  
VDD = VDDDR  
MIN.  
1.5  
TYP.  
MAX.  
3.6  
Unit  
V
Data hold current  
150  
µA  
µs  
Power supply voltage rise  
time  
tRVD  
200  
Power supply voltage fall time  
tFVD  
tHVD  
200  
0
µs  
Power supply voltage hold  
time (to STOP mode setting)  
ms  
STOP mode release signal  
input time  
tDREL  
VIHDR  
VILDR  
0
0.8 HVDDDR  
0
ns  
V
Data hold high-level input  
voltage  
Note  
Note  
VDDDR  
Data hold low-level input  
voltage  
0.2 VDDDR  
V
Note P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3,  
P34/INTP130, P35/INTP131/SO2, P36/INTP132/SI2, P37/INTP133/SCK2, P104/INTP120/TC0 to  
P107/INTP123/TC3, P114/INTP140, P115/INTP141/SO3, P116/INTP142/SI3, P117/INTP143/SCK3,  
P124/INTP150 to P126/INTP152, P127/INTP153/ADTRG, P02/TCLR10, P12/TCLR11, P32/TCLR13,  
P102/TCLR12, P112/TCLR14, P122/TCLR15, P03/TI10, P13/TI11, P33/TI13, P103/TI12, P113/TI14,  
P123/TI15, P20/NMI, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, MODE0 to MODE2, RESET  
Remark TYP. values are reference values for when TA = 25°C.  
STOP mode setting  
VDDDR  
VDD  
t
FVD  
t
RVD  
t
HVD  
t
DREL  
HVDD  
V
IHDR  
RESET (input)  
NMI (input)  
VIHDR  
(Released by falling edge)  
NMI (input)  
(Released by rising edge)  
V
ILDR  
74  
Preliminary Data Sheet U14168EJ2V0DS00  
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