µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
Load Condition
DUT
(Measured device)
CL = 50 pF
Caution In cases where the load capacitance is greater than 50 pF due to the circuit configuration, insert
a buffer or other element to reduce the device's load capacitance to 50 pF or lower.
(1) Clock timing
Parameter
X1 input cycle
Symbol
Condition
MIN.
12.5
15
MAX.
250
250
50
Unit
ns
<1>
tCYX
Direct
mode
µPD703100A-40
µPD703100A-33
ns
µ
PD703101A-33,
PD 703102A-33,
15
ns
µ
PLL mode
µPD703100A-40
PD703100A-33,
125
150
250
250
ns
ns
µ
703101A-33,
703102-A33
X1 input high-level width
X1 input low-level width
X1 input rise time
<2>
<3>
<4>
<5>
–
tWXH
tWXL
tXR
tXF
Direct mode
PLL mode
Direct mode
PLL mode
Direct mode
PLL mode
Direct mode
PLL mode
5
50
5
ns
ns
ns
50
ns
4
ns
10
4
ns
X1 input fall time
ns
10
40
33
33
500
500
100
ns
CPU operating frequency
φ
µPD703100A-40
2
2
MHz
MHz
MHz
ns
µPD703100A-33
µPD703101A-33, 703102A-33
µPD703100A-40
10
CLKOUT output cycle
<6>
tCYK
25
µPD703100A-33
30
ns
µPD703101A-33, 703102A-33
30
ns
CLKOUT input high-level width
CLKOUT input low-level width
CLKOUT input rise time
<7>
<8>
tWKH
tWKL
tKR
0.5T – 7
0.5T – 4
ns
ns
<9>
5
5
ns
CLKOUT input fall time
<10>
tKF
ns
Remark T = tCYK
76
Preliminary Data Sheet U14168EJ2V0DS00
NEC [ NEC ]
