µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
9. CLOCK GENERATION FUNCTIONS
{ Multiplier function using a PLL (Phase locked loop) synthesizer
{ Clock sources
•
•
Oscillation by connecting an oscillator: fXX = φ/5
External clock: fXX = 2 × φ or φ/5
{ Power saving modes
•
•
•
•
HALT mode
IDLE mode
Software STOP mode
Clock output inhibit mode
{ Internal system clock output function
Figure 9-1. Block Diagram of Clock Generation Function
φ
X1
CPU, on-chip peripheral I/O
CLKOUT
(fXX
)
Clock generator
(CG)
X2
CKSEL
Time base counter (TBC)
Remark φ: internal system clock frequency
FXX: external oscillator or external clock frequency
36
Preliminary Data Sheet U14168EJ2V0DS00
NEC [ NEC ]
