µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
Table 8-1. List of Interrupts (3/3)
Interrupt/Exception Source
Default Exception
Handler
Address
Restore
PC
Type
Category
Control
Generating
Unit
Priority
Code
Name
Generation Source
Register
Maskable
Interrupt
Interrupt
Interrupt
INTSR0
SRIC0
STIC0
CSIC1
UART0 receive
completion
SIO
SIO
SIO
38
0320H
00000320H
00000330H
00000340H
nextPC
nextPC
nextPC
INTST0
UART0 send
completion
39
40
0330H
0340H
INTCSI1
CSI1 send/receive
completion
Interrupt
Interrupt
INTSER1
INTSR1
SEIC1
SRIC1
UART1 receive error
SIO
SIO
41
42
0350H
0360H
00000350H
00000360H
nextPC
nextPC
UART1 receive
completion
Interrupt
Interrupt
Interrupt
Interrupt
INTST1
INTCSI2
INTCSI3
INTAD
STIC1
CSIC2
CSIC3
ADIC
UART1 send
completion
SIO
SIO
SIO
ADC
43
44
45
46
0370H
0380H
03C0H
0400H
00000370H
00000380H
000003C0H
00000400H
nextPC
nextPC
nextPC
nextPC
CSI2 send/receive
completion
CSI3 send/receive
completion
A/D conversion
completion
Remarks 1. Default priority: The priority that takes precedence when two or more maskable interrupt requests
having the same priority level are generated at the same time. The highest priority
is 0.
Restore PC: The PC value that is saved in EIPC or FEPC when the interrupt or exception
processing is started. However, the restore PC value that is saved when an interrupt is
acknowledged during the execution of a division instruction (DIV, DIVH, DIVU, or
DIVHU) is the PC value of the current instruction (DIV, DIVH, DIVU, or DIVHU).
2. The execution address of the illegal instruction when an illegal opcode exception occurs is obtained
according to the calculation “restore PC - 4.”
35
Preliminary Data Sheet U14168EJ2V0DS00
NEC [ NEC ]
