µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
Figure 10-1. Block Diagram of Timer 1 (16-bit Timer/Event Counter)
Internal system
TM10
φ
clock ( )
TCLR10
TI10
Edge detection
ETI10
Clear and
count control
Clear and
start
PRS100,
PRS101
Note 2
PRM
101
Edge detection
OVF10
φ
m
1/2
1/4
INTOV10
TM10 (16 bits)
Note 1
1/4
1/8
1/16
ALV101 ALV100
INTP100
INTP101
INTP102
INTP103
S
R
Q
CC100
CC101
CC102
CC103
TO100
TO101
Note 3 Q
Edge
detection
(INTM1)
Noise
elimination
S
RNote 3
Q
Q
IMS100 IMS101 IMS102 IMS103
INTP100/INTCC100
INTP101/INTCC101
INTP102/INTCC102
INTP103/INTCC103
Selector
Selector
Selector
Selector
TCLR11
TI11
INTP110
INTP111
INTP112
INTP113
INTOV11
TO110
TO111
TM11
INTP110/INTCC110
INTP111/INTCC111
INTP112/INTCC112
INTP113/INTCC113
TCLR15
TI15
INTP150
INTP151
INTP152
INTP153
INTOV15
TO150
TO151
TM15
INTP150/INTCC150
INTP151/INTCC151
INTP152/INTCC152
INTP153/INTCC153
Notes 1. Internal count clock
2. External count clock
3. Reset priority
38
Preliminary Data Sheet U14168EJ2V0DS00
NEC [ NEC ]
