µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
(12) CSI0 to CSI3 timing
(a) Master mode
Parameter
SCKn cycle
Symbol
<147>
Condition
Output
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
tCYSK1
tWSK1H
tWSK1L
tSSISK
100
SCKn high-level width
<148>
<149>
<150>
<151>
<152>
<153>
Output
0.5tCYSK1 – 20
SCKn low-level width
Output
0.5tCYSK1 – 20
SIn setup time (to SCKn ↑)
SIn hold time (from SCKn ↑)
SOn output delay time (from SCKn ↓)
SOn output hold time (from SCKn ↑)
30
0
tHSKSI
tDSKSO
tHSKSO
20
0.5tCYSK1 – 5
Remark n = 0 to 3
(b) Slave mode
Parameter
SCKn cycle
Symbol
Condition
Input
MIN.
100
30
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
<147>
<148>
<149>
<150>
<151>
<152>
<153>
tCYSK1
tWSK1H
tWSK1L
tSSISK
SCKn high-level width
Input
SCKn low-level width
Input
30
SIn setup time (to SCKn ↑)
SIn hold time (from SCKn ↑)
SOn output delay time (from SCKn ↓)
SOn output hold time (from SCKn ↑)
10
tHSKSI
tDSKSO
tHSKSO
10
30
tWSK1H
Remark n = 0 to 3
<147>
<149>
<148>
SCKn (I/O)
<150>
<151>
Sln (Input)
Input data
<152>
<153>
SOn (Output)
Output data
Remarks 1. The broken lines indicate high impedance.
2. n = 0 to 3
124
Preliminary Data Sheet U14168EJ2V0DS00
NEC [ NEC ]
