µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
(8) Bus hold timing (1/2)
Parameter
Symbol
Condition
MIN.
10
MAX.
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
HLDRQ setup time (to CLKOUT ↑)
HLDRQ hold time (from CLKOUT ↑)
HLDAK delay time from CLKOUT ↓
HLDRQ high-level width
<123>
tSHRK
tHKHR
<124>
<125>
<126>
<127>
<128>
<129>
<130>
<131>
5
tDKHA
2
tWHQH
tWHAL
tDKCF
T + 17
T – 8
HLDAK low-level width
Bus float delay time from CLKOUT ↓
Bus output delay time from HLDAK ↑
HLDAK ↓ delay time from HLDRQ ↓
HLDAK ↑ delay time from HLDRQ ↑
10
tDHAC
0
tDHQHA1
tDHQHA2
2.5T
0.5T
1.5T
Remark T = tCYK
120
Preliminary Data Sheet U14168EJ2V0DS00