Figure 13-1. Block Diagram of LCD Controller/Driver
Internal bus
LCD clock control
register 0 (LCDC0)
LCD display mode
register 0 (LCDM0)
LCD voltage amplification
control register 0 (LCDVA0)
Display data memory
FA04H
(FA0EH)Note
7 6 5 4 3 2 1 0
FA00H
LCDON0
LCDM00
LCDC03 LCDC02 LCDC01 LCDC00
LIPS0 LCDM02 LCDM01
GAIN
VAON0
7 6 5 4 3 2 1 0
2
2
3
fX
fX
fX
/25
/26
/27
f
LCD
Prescaler
f
XT
f
CLK
26
f
CLK
f
CLK
f
CLK
29
27
28
LCD
clock
selector
3 2 1 0
Selector
3 2 1 0
Selector
LCDCL
Timing
controller
LCDON0
LCDON0
Voltage
amplifier
Segment
driver
Segment
driver
LCD drive voltage controller
Common driver
VLC1
VLC2
VLC0
COM0 COM1 COM2 COM3
S4
S0
(S14)
Note The parenthesized values apply to the
µ
PD789446 and 789456 Subseries.
NEC [ NEC ]
