MUPA64K16 Alto Priority Queue Scheduler
Table 2: Registers
Register
Description
R/W
Size
Reg[2:0]
/W
Input Data Register
(IDR)
Contains the associated data value
for the next INSERT or BOTH
instruction
W
16
1
0
Input Key Register
(IKR)
Minimum Data
Register
Contains the key value for the next
INSERT or BOTH instruction
Contains the data associated with the
minimum key value returned by a
PEEK, EXTRACT or BOTH
instruction
W
R
32
16
0
1
0
1
(MDR)
Minimum Key Register Contains the minimum key value
(MKR)
returned by the PEEK, EXTRACT or
BOTH instruction
R
32
0
1
Size Registers (16)
(SR)
Wrap Registers (16)
(WR)
Indicates the size of each of the
priority queues
Holds the value that is to be
considered minimum
R/W
R/W
R
17
32
17
16
3
2
3
5
5
4
0/1
0/1
1
UID Get Registers (16) Holds the next available unique
(UGR)
UID Put Register
(UPR)
identifier that is not in use
Accepts identifiers that are no longer
in use to be returned to the free list
Determines the number of
independent priority queues in use: 1,
2 4, 8 or 16
W
0
Mode Register (MR)
R/W
0/1
Status Register (STR) Provides device status
Reserved
R
21
6
7
1
R/W
N/A
0/1
UID Put
Register
Input Data
Register
Input Key
Register
Mode
Register
Wrap
Register x16
Size
Register x16
Status
Register
UID Get
Register x16
Min Data
Register
Min Key
Register
PQ[3:0]
MUX
MUX
PQ[3:0]
PQ[3:0]
MUX
MUX
STR[4:0]
ADS
MUX
MUX
REG[2:0]
DQ[31:0]
AD[15:0]
Figure 3: Register Datapath
MUSIC Semiconductors Confidential
5
Rev 0.3 Draft
MUSIC [ MUSIC SEMICONDUCTORS ]
